tegra video: add driver for host1x hardware

The graphics hardware modules on Tegra family of SOCs are accessed via
the host1x dma and synchronization engine. This driver exposes an
userspace interface for submitting command buffers to 2d, 3d, display
and mpe hardware modules and accessing the module register apertures
for exclusive use hardware modules.

Additional features of the driver include:
- interrupt-driven hardware module usage synchronization
- automatic clock management for hw modules
- hardware context switching for 3d registers

Change-Id: I693582249597fd307526ff3c7e35889d37406017
Reviewed-on: http://git-master/r/4091
Reviewed-by: Janne Hellsten <jhellsten@nvidia.com>
Tested-by: Janne Hellsten <jhellsten@nvidia.com>

3 files changed, 17 insertions, 160 deletions

diff --git a/arch/arm/mach-tegra/include/mach/iomap.h b/arch/arm/mach-tegra/include/mach/iomap.h
index bd28f03dd4fc..d5fb089864ad 100644
--- a/arch/arm/mach-tegra/include/mach/iomap.h
+++ b/arch/arm/mach-tegra/include/mach/iomap.h
@@ -26,6 +26,9 @@
 #define TEGRA_IRAM_BASE			0x40000000
 #define TEGRA_IRAM_SIZE			SZ_256K
 
+#define TEGRA_HOST1X_BASE		0x50000000
+#define TEGRA_HOST1X_SIZE		0x24000
+
 #define TEGRA_ARM_PERIF_BASE		0x50040000
 #define TEGRA_ARM_PERIF_SIZE		SZ_8K
 
@@ -35,6 +38,15 @@
 #define TEGRA_ARM_INT_DIST_BASE		0x50041000
 #define TEGRA_ARM_INT_DIST_SIZE		SZ_4K
 
+#define TEGRA_MPE_BASE			0x54040000
+#define TEGRA_MPE_SIZE			SZ_256K
+
+#define TEGRA_VI_BASE			0x54080000
+#define TEGRA_VI_SIZE			SZ_256K
+
+#define TEGRA_ISP_BASE			0x54100000
+#define TEGRA_ISP_SIZE			SZ_256K
+
 #define TEGRA_DISPLAY_BASE		0x54200000
 #define TEGRA_DISPLAY_SIZE		SZ_256K
 
diff --git a/arch/arm/mach-tegra/include/mach/irqs.h b/arch/arm/mach-tegra/include/mach/irqs.h
index abd8449b72d7..91388d8967fc 100644
--- a/arch/arm/mach-tegra/include/mach/irqs.h
+++ b/arch/arm/mach-tegra/include/mach/irqs.h
@@ -166,9 +166,12 @@
 #define INT_QUAD_RES_30			(INT_QUAD_BASE + 30)
 #define INT_QUAD_RES_31			(INT_QUAD_BASE + 31)
 
-#define INT_GPIO_BASE			(INT_QUAD_BASE + 32)
-#define INT_GPIO_NR			(28 * 8)
+#define INT_SYNCPT_THRESH_BASE		(INT_QUAD_BASE + 32)
+#define INT_SYNCPT_THRESH_NR		32
 
+#define INT_GPIO_BASE			(INT_SYNCPT_THRESH_BASE + \
+					 INT_SYNCPT_THRESH_NR)
+#define INT_GPIO_NR			(28 * 8)
 #endif
 
 #define NR_IRQS				(INT_GPIO_BASE + INT_GPIO_NR)
diff --git a/arch/arm/mach-tegra/include/mach/nvmem.h b/arch/arm/mach-tegra/include/mach/nvmem.h
deleted file mode 100644
index 3be28fff8856..000000000000
--- a/arch/arm/mach-tegra/include/mach/nvmem.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * arch/arm/mach-tegra/include/linux/nvmem_ioctl.h
- *
- * structure declarations for nvmem and nvmap user-space ioctls
- *
- * Copyright (c) 2009, NVIDIA Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
- */
-
-#include <linux/ioctl.h>
-
-#if !defined(__KERNEL__)
-#define __user
-#endif
-
-#ifndef _MACH_TEGRA_NVMEM_IOCTL_H_
-#define _MACH_TEGRA_NVMEM_IOCTL_H_
-
-struct nvmem_create_handle {
-	union {
-		__u32 key;	/* ClaimPreservedHandle */
-		__u32 id;	/* FromId */
-		__u32 size;	/* CreateHandle */
-	};
-	__u32 handle;
-};
-
-#define NVMEM_HEAP_SYSMEM  (1ul<<31)
-#define NVMEM_HEAP_IOVMM   (1ul<<30)
-
-/* common carveout heaps */
-#define NVMEM_HEAP_CARVEOUT_IRAM    (1ul<<29)
-#define NVMEM_HEAP_CARVEOUT_GENERIC (1ul<<0)
-
-#define NVMEM_HEAP_CARVEOUT_MASK    (NVMEM_HEAP_IOVMM - 1)
-
-#define NVMEM_HANDLE_UNCACHEABLE     (0x0ul << 0)
-#define NVMEM_HANDLE_WRITE_COMBINE   (0x1ul << 0)
-#define NVMEM_HANDLE_INNER_CACHEABLE (0x2ul << 0)
-#define NVMEM_HANDLE_CACHEABLE       (0x3ul << 0)
-
-#define NVMEM_HANDLE_SECURE          (0x1ul << 2)
-
-struct nvmem_alloc_handle {
-	__u32 handle;
-	__u32 heap_mask;
-	__u32 flags;
-	__u32 align;
-};
-
-struct nvmem_map_caller {
-	__u32 handle;		/* hmem */
-	__u32 offset;		/* offset into hmem; should be page-aligned */
-	__u32 length;		/* number of bytes to map */
-	__u32 flags;
-	unsigned long addr;	/* user pointer */
-};
-
-struct nvmem_rw_handle {
-	unsigned long addr;	/* user pointer */
-	__u32 handle;		/* hmem */
-	__u32 offset;		/* offset into hmem */
-	__u32 elem_size;	/* individual atom size */
-	__u32 hmem_stride;	/* delta in bytes between atoms in hmem */
-	__u32 user_stride;	/* delta in bytes between atoms in user */
-	__u32 count;		/* number of atoms to copy */
-};
-
-struct nvmem_pin_handle {
-	unsigned long handles;	/* array of handles to pin/unpin */
-	unsigned long addr;	/* array of addresses to return */
-	__u32 count;		/* number of entries in handles */
-};
-
-struct nvmem_handle_param {
-	__u32 handle;
-	__u32 param;
-	unsigned long result;
-};
-
-enum {
-	NVMEM_HANDLE_PARAM_SIZE = 1,
-	NVMEM_HANDLE_PARAM_ALIGNMENT,
-	NVMEM_HANDLE_PARAM_BASE,
-	NVMEM_HANDLE_PARAM_HEAP,
-};
-
-enum {
-	NVMEM_CACHE_OP_WB = 0,
-	NVMEM_CACHE_OP_INV,
-	NVMEM_CACHE_OP_WB_INV,
-};
-
-struct nvmem_cache_op {
-	unsigned long addr;
-	__u32 handle;
-	__u32 len;
-	__s32 op;
-};
-
-#define NVMEM_IOC_MAGIC 'N'
-
-/* Creates a new memory handle. On input, the argument is the size of the new
- * handle; on return, the argument is the name of the new handle
- */
-#define NVMEM_IOC_CREATE  _IOWR(NVMEM_IOC_MAGIC, 0, struct nvmem_create_handle)
-#define NVMEM_IOC_CLAIM   _IOWR(NVMEM_IOC_MAGIC, 1, struct nvmem_create_handle)
-#define NVMEM_IOC_FROM_ID _IOWR(NVMEM_IOC_MAGIC, 2, struct nvmem_create_handle)
-
-/* Actually allocates memory for the specified handle */
-#define NVMEM_IOC_ALLOC    _IOW (NVMEM_IOC_MAGIC, 3, struct nvmem_alloc_handle)
-
-/* Frees a memory handle, unpinning any pinned pages and unmapping any mappings
- */
-#define NVMEM_IOC_FREE       _IO (NVMEM_IOC_MAGIC, 4)
-
-/* Maps the region of the specified handle into a user-provided virtual address
- * that was previously created via an mmap syscall on this fd */
-#define NVMEM_IOC_MMAP       _IOWR(NVMEM_IOC_MAGIC, 5, struct nvmem_map_caller)
-
-/* Reads/writes data (possibly strided) from a user-provided buffer into the
- * hmem at the specified offset */
-#define NVMEM_IOC_WRITE      _IOW (NVMEM_IOC_MAGIC, 6, struct nvmem_rw_handle)
-#define NVMEM_IOC_READ       _IOW (NVMEM_IOC_MAGIC, 7, struct nvmem_rw_handle)
-
-#define NVMEM_IOC_PARAM _IOWR(NVMEM_IOC_MAGIC, 8, struct nvmem_handle_param)
-
-/* Pins a list of memory handles into IO-addressable memory (either IOVMM
- * space or physical memory, depending on the allocation), and returns the
- * address. Handles may be pinned recursively. */
-#define NVMEM_IOC_PIN_MULT   _IOWR(NVMEM_IOC_MAGIC, 10, struct nvmem_pin_handle)
-#define NVMEM_IOC_UNPIN_MULT _IOW (NVMEM_IOC_MAGIC, 11, struct nvmem_pin_handle)
-
-#define NVMEM_IOC_CACHE      _IOW (NVMEM_IOC_MAGIC, 12, struct nvmem_cache_op)
-
-/* Returns a global ID usable to allow a remote process to create a handle
- * reference to the same handle */
-#define NVMEM_IOC_GET_ID  _IOWR(NVMEM_IOC_MAGIC, 13, struct nvmem_create_handle)
-
-#define NVMEM_IOC_MAXNR (_IOC_NR(NVMEM_IOC_GET_ID))
-
-int nvmap_add_carveout_heap(unsigned long base, size_t size,
-	const char *name, unsigned int bitmask);
-
-#endif