diff options
| author | Daehyoung Ko <dko@nvidia.com> | 2011-09-30 17:42:49 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:49:35 -0800 |
| commit | 52b6d9eb2a5fd416db74102f366f0ee4bef60af3 (patch) | |
| tree | 65bf15d5319c6a4d5933c3fd4700ee82a7fd8119 /arch/arm/mach-tegra/irq.c | |
| parent | f20df7895e9c2a8e0ebbd8c806666be3ddf04d61 (diff) | |
ARM tegra: gpio: Correct gpio interrupt init sequence
It is possible for GPIO interrupt to occur when registering handler
since set_irq_chained_handler enables GPIO interrupt. Thus
all relevant variables are required to be initialized
before calling set_irq_chained_handler.
Also add initialization of interrupt status register.
Bug 884569
Reviewed-on: http://git-master/r/58218
(cherry picked from commit e03fe4cc1bf06fa6c32c0520e2ba31f009f9301d)
Change-Id: Ic76f95215b61d6e091ae1cfa11522f8af9c3eecd
Reviewed-on: http://git-master/r/60475
Reviewed-by: Daehyoung Ko <dko@nvidia.com>
Tested-by: Daehyoung Ko <dko@nvidia.com>
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Rebase-Id: R5340918dccc1a8b1d95c5b629cc985f44d45fb67
Diffstat (limited to 'arch/arm/mach-tegra/irq.c')
| -rw-r--r-- | arch/arm/mach-tegra/irq.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c index 570c699f064a..e989d19a2fa4 100644 --- a/arch/arm/mach-tegra/irq.c +++ b/arch/arm/mach-tegra/irq.c @@ -197,6 +197,7 @@ void __init tegra_init_irq(void) void __iomem *ictlr = ictlr_reg_base[i]; writel(~0, ictlr + ICTLR_CPU_IER_CLR); writel(0, ictlr + ICTLR_CPU_IEP_CLASS); + writel(~0, ictlr + ICTLR_CPU_IEP_FIR_CLR); } gic_arch_extn.irq_ack = tegra_ack; |