diff options
| author | Kaz Fukuoka <kfukuoka@nvidia.com> | 2011-05-25 18:21:32 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:48:26 -0800 |
| commit | 95ad04c37e78fe9de4a8c467e187d732a02a6033 (patch) | |
| tree | 5e3c1d247701ede34bef8f6d98c6f5394636594e /arch/arm/mach-tegra/irq.c | |
| parent | d71d77427dea3f95ce003c0a4a8b6f2ddabf10ca (diff) | |
media: tegra: avp: Clear interrupt registers when AVP starts
There was no code to clear interrupt registers for AVP. First run
of AVP was OK because those registers start from reset value.
But because those registers were not cleared, when the second
time AVP was started, some interrupts were enabled too early.
That caused interrupts coming before handlers were ready.
This change also removes the workaroud for the bug.
bug 827353
bug 826234
Original-Change-Id: I51546400f0bace67dfcdb23f667c051c060d3983
Reviewed-on: http://git-master/r/33083
Reviewed-by: Niket Sirsi <nsirsi@nvidia.com>
Tested-by: Niket Sirsi <nsirsi@nvidia.com>
Rebase-Id: Rb45b8d54afeda71d35c011120fc0e748929ad74e
Diffstat (limited to 'arch/arm/mach-tegra/irq.c')
| -rw-r--r-- | arch/arm/mach-tegra/irq.c | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c index 59472fb39430..570c699f064a 100644 --- a/arch/arm/mach-tegra/irq.c +++ b/arch/arm/mach-tegra/irq.c @@ -26,6 +26,7 @@ #include <asm/hardware/gic.h> #include <mach/iomap.h> +#include <mach/legacy_irq.h> #include "board.h" #include "pm-irq.h" @@ -210,3 +211,14 @@ void __init tegra_init_irq(void) gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE), IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100)); } + +void tegra_init_legacy_irq_cop(void) +{ + int i; + + for (i = 0; i < NUM_ICTLRS; i++) { + void __iomem *ictlr = ictlr_reg_base[i]; + writel(~0, ictlr + ICTLR_COP_IER_CLR); + writel(0, ictlr + ICTLR_COP_IEP_CLASS); + } +} |