diff options
| author | Michael Frydrych <mfrydrych@nvidia.com> | 2012-07-11 11:43:42 +0300 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 12:15:07 -0700 |
| commit | 029d7fc048e953a9bbec12411627a63e16676c52 (patch) | |
| tree | f52744b7e28edef8a5c998918291a2dfc3d185e6 /arch/arm/mach-tegra/latency_allowance.c | |
| parent | 59e4124d6dcaa70bbfcf5af7661c031f9b3dab10 (diff) | |
arm: tegra: la: hack latency allowance formula
Remove the ad-hoc scale factor of final latency allowance.
Scale the fifo size to pretend that our FIFO is only as deep
as the lowest fullness we expect to see.
Bug 995270
Change-Id: I78ed2246d2031a2303f81a19fe05c95572a692b0
Signed-off-by: Michael Frydrych <mfrydrych@nvidia.com>
Reviewed-on: http://git-master/r/118816
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-by: Graziano Misuraca <gmisuraca@nvidia.com>
Tested-by: Graziano Misuraca <gmisuraca@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Rebase-Id: R32a6b53f3eed710c019b14d30703c58f8e7c5852
Diffstat (limited to 'arch/arm/mach-tegra/latency_allowance.c')
| -rw-r--r-- | arch/arm/mach-tegra/latency_allowance.c | 22 |
1 files changed, 15 insertions, 7 deletions
diff --git a/arch/arm/mach-tegra/latency_allowance.c b/arch/arm/mach-tegra/latency_allowance.c index 27fd0339f6c5..91eeed3c0365 100644 --- a/arch/arm/mach-tegra/latency_allowance.c +++ b/arch/arm/mach-tegra/latency_allowance.c @@ -1,7 +1,7 @@ /* * arch/arm/mach-tegra/latency_allowance.c * - * Copyright (C) 2011 NVIDIA Corporation + * Copyright (C) 2011-2012, NVIDIA CORPORATION. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -100,6 +100,9 @@ printk(KERN_INFO pr_fmt(fmt), ##__VA_ARGS__); \ } +/* Bug 995270 */ +#define HACK_LA_FIFO 1 + static struct dentry *latency_debug_dir; struct la_client_info { @@ -387,7 +390,9 @@ int tegra_set_latency_allowance(enum tegra_la_id id, int la_to_set; unsigned long reg_read; unsigned long reg_write; + unsigned int fifo_size_in_atoms; int bytes_per_atom = normal_atom_size; + const int fifo_scale = 4; /* 25% of the FIFO */ struct la_client_info *ci; VALIDATE_ID(id); @@ -397,11 +402,19 @@ int tegra_set_latency_allowance(enum tegra_la_id id, bytes_per_atom = fdc_atom_size; ci = &la_info[id]; + fifo_size_in_atoms = ci->fifo_size_in_atoms; + +#if HACK_LA_FIFO + /* pretend that our FIFO is only as deep as the lowest fullness + * we expect to see */ + if (id >= ID(DISPLAY_0A) && id <= ID(DISPLAY_HCB)) + fifo_size_in_atoms /= fifo_scale; +#endif if (bandwidth_in_mbps == 0) { la_to_set = MC_LA_MAX_VALUE; } else { - ideal_la = (ci->fifo_size_in_atoms * bytes_per_atom * 1000) / + ideal_la = (fifo_size_in_atoms * bytes_per_atom * 1000) / (bandwidth_in_mbps * ns_per_tick); la_to_set = ideal_la - (ci->expiration_in_ns/ns_per_tick) - 1; } @@ -412,11 +425,6 @@ int tegra_set_latency_allowance(enum tegra_la_id id, la_to_set = (la_to_set > MC_LA_MAX_VALUE) ? MC_LA_MAX_VALUE : la_to_set; scaling_info[id].actual_la_to_set = la_to_set; - /* until display can use latency allowance scaling, use a more - * aggressive LA setting. Bug 862709 */ - if (id >= ID(DISPLAY_0A) && id <= ID(DISPLAY_HCB)) - la_to_set /= 3; - spin_lock(&safety_lock); reg_read = readl(ci->reg_addr); reg_write = (reg_read & ~ci->mask) | |