diff options
| author | Xin Xie <xxie@nvidia.com> | 2011-07-07 14:05:04 -0700 |
|---|---|---|
| committer | Varun Colbert <vcolbert@nvidia.com> | 2011-07-26 16:53:00 -0700 |
| commit | 54445ff6b7305bead87a79d60c4781d66f7cef18 (patch) | |
| tree | 946b7512fd0a6b3cc21c849ae28b741bce7bfdd0 /arch/arm/mach-tegra/mc.c | |
| parent | 74f141a4702ff0edea6c473f182905ebd8ac4acb (diff) | |
video: tegra: dc: fix tiled memory efficiency
Tegra3 also supports LPDDR2 which has no tiled memory inefficiency as in DDR3.
This patch adds one memory controller API to retrive tiled memory efficiency.
BUG 847731
Change-Id: I407914c6035389b696040947e7aebc6ecdb92bb1
Reviewed-on: http://git-master/r/40074
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/mc.c')
| -rw-r--r-- | arch/arm/mach-tegra/mc.c | 27 |
1 files changed, 26 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/mc.c b/arch/arm/mach-tegra/mc.c index 57b2f6f4e223..4f2c7dac551f 100644 --- a/arch/arm/mach-tegra/mc.c +++ b/arch/arm/mach-tegra/mc.c @@ -42,6 +42,31 @@ void tegra_mc_set_priority(unsigned long client, unsigned long prio) spin_unlock_irqrestore(&tegra_mc_lock, flags); } + +int tegra_mc_get_tiled_memory_bandwidth_multiplier(void) +{ + return 1; +} + #else - /* !!!FIXME!!! IMPLEMENT ME */ + /* !!!FIXME!!! IMPLEMENT tegra_mc_set_priority() */ + +#include "tegra3_emc.h" + +/* + * If using T30/DDR3, the 2nd 16 bytes part of DDR3 atom is 2nd line and is + * discarded in tiling mode. + */ +int tegra_mc_get_tiled_memory_bandwidth_multiplier(void) +{ + int type; + + type = tegra_emc_get_dram_type(); + WARN_ONCE(type == -1, "unknown type DRAM because DVFS is disabled\n"); + + if (type == DRAM_TYPE_DDR3) + return 2; + else + return 1; +} #endif |