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author | Laxman Dewangan <ldewangan@nvidia.com> | 2010-06-12 14:12:28 +0530 |
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committer | Gary King <gking@nvidia.com> | 2010-06-14 11:11:36 -0700 |
commit | df3a2907764ad602865870e03f606488cda20514 (patch) | |
tree | 138902a5639aab351f28028e00e90f518fbd6f56 /arch/arm/mach-tegra/nvddk/nvddk_aes_priv.h | |
parent | 69074ee65d452cae27719559c8fe50c8d1b80e75 (diff) |
[ARM/tegra] spi: Adding support for the hw based CS.
It is require to use the hw based CS to meet the timing requirement as:
- Minimum CS setup time i.e. time from CS active to first clock.
- Maximum CS hold time i.e. CS should be active after last clock.
SW based CS can support the above 1 but not 2 because it dpeneds on os
load and system performance. To meet the above requirements, it is
require to enable the hw based CS.
As spi controller support for the hw based CS for the smaller number
of packet, enabling this feature.
Driver use the sw based CS by default. If client want to use the hw
based CS, then it need to enable this through nvodm query
NvOdmQuerySpiDeviceInfo table for different CS.
For this, client need to set device info as
CanUseHwBasedCs = TRUE,
CsSetupTimeInClock = xx
CsHoldTimeInClock = xx
Change-Id: I9e943e0b39f2d75272826cc2ec7687b3434b1c2a
Reviewed-on: http://git-master/r/2536
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/nvddk/nvddk_aes_priv.h')
0 files changed, 0 insertions, 0 deletions