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authorAlex Frid <afrid@nvidia.com>2010-07-21 18:35:39 -0700
committerGary King <gking@nvidia.com>2010-07-22 08:21:24 -0700
commitbd678487f1dcb3964a5cb4d16a93e2defb0a0d5f (patch)
treeb15df2bbc828f0e302d4700d53f3b8dceba2a88f /arch/arm/mach-tegra/nvrm
parent4df5e85aac6f8f954963d6779b81dd604613ef2b (diff)
[ARM/tegra] RM: added LP2 configuration options.
Added configuration options to set default LP2 policy. Change-Id: I81820f575858dda62d31b304b6adf09f7d0f3689 Reviewed-on: http://git-master/r/4164 Tested-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Gary King <gking@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/nvrm')
-rw-r--r--arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.c2
-rw-r--r--arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.h4
2 files changed, 0 insertions, 6 deletions
diff --git a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.c b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.c
index af6c0309a8d1..985f8df19643 100644
--- a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.c
+++ b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.c
@@ -74,12 +74,10 @@ void NvRmPrivAp20EmcParametersAdjust(NvRmDfs* pDfs)
{
case EMC_FBIO_CFG5_0_DRAM_TYPE_LPDDR2:
pDfs->DfsParameters[NvRmDfsClockId_Emc] = EmcParamLpDddr2;
- g_Lp2Policy = NVRM_AP20_LPDDR2_LP2POLICY;
break;
case EMC_FBIO_CFG5_0_DRAM_TYPE_DDR2:
pDfs->DfsParameters[NvRmDfsClockId_Emc] = EmcParamDddr2;
- g_Lp2Policy = NVRM_AP20_DDR2_LP2POLICY;
break;
default:
diff --git a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.h b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.h
index 3d8c85be21c5..8b5c9d4ded39 100644
--- a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.h
+++ b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.h
@@ -233,10 +233,6 @@ extern "C"
#define NVRM_DFS_PARAM_EMC_AP20 NVRM_DFS_PARAM_EMC_AP20_LPDDR2
-// Defines LP2 entry policy each supported SDRAM type
-#define NVRM_AP20_DDR2_LP2POLICY (NvRmLp2Policy_IgnoreLowCorner)
-#define NVRM_AP20_LPDDR2_LP2POLICY (NvRmLp2Policy_MaskInLowCorner)
-
/**
* Defines CPU frequency threshold for slave CPU1 power management:
* - CPU1 is turned Off when cpu clock is below ON_MIN for