diff options
| author | Alex Frid <afrid@nvidia.com> | 2010-07-07 21:01:44 -0700 |
|---|---|---|
| committer | Gary King <gking@nvidia.com> | 2010-07-13 12:34:54 -0700 |
| commit | 32efa0b83a91b12a0df1b37550a9d154b9c907ce (patch) | |
| tree | 671a2699ca19c070b0104034bc76ee9dbf8022d6 /arch/arm/mach-tegra/nvrm | |
| parent | dbd3ac0d44a05815bfa6f40130844012dbac5c42 (diff) | |
[ARM/tegra] RM: Set LP2 policies per SDRAM type.
Set different LP2 policies based on SDRAM typed:
- "Ignore Low Corner" for DDR2 platforms (no changes, since DDR2
scaling is limited).
- "Mask in Low Corner" for LPDDR2 platforms - changed so that DVFS
continue to run until LPDDR2 frequency reaches low corner.
This change should compensate increase in core/SDRAM power observed
for low power use cases after switch to 2.6.32 kernel (bug 697013).
Change-Id: I5f6ed7196bb03bd3182d858760c50f2072afe494
Reviewed-on: http://git-master.nvidia.com/r/3654
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Narendra Damahe <ndamahe@nvidia.com>
Reviewed-by: Sharad Ranjan <shranjan@nvidia.com>
Tested-by: Dara Ramesh <dramesh@nvidia.com>
Reviewed-by: Gary King <gking@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/nvrm')
| -rw-r--r-- | arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.c | 4 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.h | 4 |
2 files changed, 8 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.c b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.c index 633e0df67604..af6c0309a8d1 100644 --- a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.c +++ b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.c @@ -68,14 +68,18 @@ void NvRmPrivAp20EmcParametersAdjust(NvRmDfs* pDfs) NvU32 RegValue = NV_REGR(pDfs->hRm, NvRmPrivModuleID_ExternalMemoryController, 0, EMC_FBIO_CFG5_0); + // Overwrite default EMC parameters and LP2 policy with SDRAM type specific + // settings switch (NV_DRF_VAL(EMC, FBIO_CFG5, DRAM_TYPE, RegValue)) { case EMC_FBIO_CFG5_0_DRAM_TYPE_LPDDR2: pDfs->DfsParameters[NvRmDfsClockId_Emc] = EmcParamLpDddr2; + g_Lp2Policy = NVRM_AP20_LPDDR2_LP2POLICY; break; case EMC_FBIO_CFG5_0_DRAM_TYPE_DDR2: pDfs->DfsParameters[NvRmDfsClockId_Emc] = EmcParamDddr2; + g_Lp2Policy = NVRM_AP20_DDR2_LP2POLICY; break; default: diff --git a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.h b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.h index 8b5c9d4ded39..3d8c85be21c5 100644 --- a/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.h +++ b/arch/arm/mach-tegra/nvrm/core/ap20/ap20rm_power_dfs.h @@ -233,6 +233,10 @@ extern "C" #define NVRM_DFS_PARAM_EMC_AP20 NVRM_DFS_PARAM_EMC_AP20_LPDDR2 +// Defines LP2 entry policy each supported SDRAM type +#define NVRM_AP20_DDR2_LP2POLICY (NvRmLp2Policy_IgnoreLowCorner) +#define NVRM_AP20_LPDDR2_LP2POLICY (NvRmLp2Policy_MaskInLowCorner) + /** * Defines CPU frequency threshold for slave CPU1 power management: * - CPU1 is turned Off when cpu clock is below ON_MIN for |