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authorJon Mayo <jmayo@nvidia.com>2010-09-09 11:46:18 -0700
committerVarun Colbert <vcolbert@nvidia.com>2010-10-26 15:03:36 -0700
commit35e97aa59eaa0cc7233c100edc0aa3e7b4e1605e (patch)
tree743512854b2ce749bd92eb09c6ae52688b8ff1a8 /arch/arm/mach-tegra/odm_kit/adaptations/pmu/pmu_hal.c
parentdc9cea61b3333432d6c1d2003a1bdb9ce055f04a (diff)
[arm/tegra] support RTC alarm interrupt in odm_kit
New API added to odm_kit to register a callback to use on RTC interrupt. Supported added for RTC alarms in the max8907b PMU. Bug 717253 Bug 734529 Change-Id: I34abebd7dd3caf4ef8923fcf651c50f6d245f6b4 Reviewed-on: http://git-master/r/7328 Reviewed-by: Krishna Reddy <vdumpa@nvidia.com> Reviewed-by: Jonathan Mayo <jmayo@nvidia.com> Tested-by: Jonathan Mayo <jmayo@nvidia.com> Reviewed-by: Aleksandr Frid <afrid@nvidia.com> Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com> Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/odm_kit/adaptations/pmu/pmu_hal.c')
-rw-r--r--arch/arm/mach-tegra/odm_kit/adaptations/pmu/pmu_hal.c53
1 files changed, 46 insertions, 7 deletions
diff --git a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pmu_hal.c b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pmu_hal.c
index ffe0b584340d..95075edf30c0 100644
--- a/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pmu_hal.c
+++ b/arch/arm/mach-tegra/odm_kit/adaptations/pmu/pmu_hal.c
@@ -72,11 +72,15 @@ GetPmuInstance(NvOdmPmuDeviceHandle hDevice)
Pmu.pfnWriteRtc = Tps6586xWriteRtc;
Pmu.pfnReadAlarm = Tps6586xReadAlarm;
Pmu.pfnWriteAlarm = Tps6586xWriteAlarm;
+ Pmu.pfnAlarmInterrupt = NULL;
+ Pmu.pfnEnableRtcInt = NULL;
+ Pmu.pfnSuspendRtc = NULL;
+ Pmu.pfnResumeRtc = NULL;
Pmu.pfnIsRtcInitialized = Tps6586xIsRtcInitialized;
}
else if (NvOdmPeripheralGetGuid(NV_ODM_GUID('p','c','f','_','p','m','u','0')))
{
-
+
Pmu.pfnSetup = Pcf50626Setup;
Pmu.pfnRelease = Pcf50626Release;
Pmu.pfnGetCaps = Pcf50626GetCapabilities;
@@ -93,9 +97,13 @@ GetPmuInstance(NvOdmPmuDeviceHandle hDevice)
Pmu.pfnWriteRtc = Pcf50626RtcCountWrite;
Pmu.pfnReadAlarm = NULL;
Pmu.pfnWriteAlarm = NULL;
+ Pmu.pfnAlarmInterrupt = NULL;
+ Pmu.pfnEnableRtcInt = NULL;
+ Pmu.pfnSuspendRtc = NULL;
+ Pmu.pfnResumeRtc = NULL;
Pmu.pfnIsRtcInitialized = Pcf50626IsRtcInitialized;
- Pmu.pPrivate = NULL;
- Pmu.Hal = NV_TRUE;
+ Pmu.pPrivate = NULL;
+ Pmu.Hal = NV_TRUE;
Pmu.Init = NV_FALSE;
}
else if (NvOdmPeripheralGetGuid(NV_ODM_GUID('m','a','x','8','9','0','7','b')))
@@ -115,11 +123,15 @@ GetPmuInstance(NvOdmPmuDeviceHandle hDevice)
Pmu.pfnInterruptHandler = Max8907bInterruptHandler;
Pmu.pfnReadRtc = Max8907bRtcCountRead;
Pmu.pfnWriteRtc = Max8907bRtcCountWrite;
- Pmu.pfnReadAlarm = NULL;
- Pmu.pfnWriteAlarm = NULL;
+ Pmu.pfnReadAlarm = Max8907bRtcAlarmCountRead;
+ Pmu.pfnWriteAlarm = Max8907bRtcAlarmCountWrite;
+ Pmu.pfnAlarmInterrupt = NULL;
+ Pmu.pfnEnableRtcInt = Max8907bRtcAlarmIntEnable;
+ Pmu.pfnSuspendRtc = Max8907bRtcSuspend;
+ Pmu.pfnResumeRtc = Max8907bRtcResume;
Pmu.pfnIsRtcInitialized = Max8907bIsRtcInitialized;
Pmu.pPrivate = NULL;
- Pmu.Hal = NV_TRUE;
+ Pmu.Hal = NV_TRUE;
Pmu.Init = NV_FALSE;
}
}
@@ -376,7 +388,34 @@ NvOdmPmuIsRtcInitialized(NvOdmPmuDeviceHandle hDevice)
if (pmu && pmu->pfnIsRtcInitialized)
return pmu->pfnIsRtcInitialized(pmu);
-
+
return NV_FALSE;
}
+NvBool
+NvOdmPmuAlarmHandlerSet(NvOdmPmuDeviceHandle hDevice, pfnPmuAlarmInterrupt func)
+{
+ NvOdmPmuDevice *pmu = GetPmuInstance(hDevice);
+ if (!pmu)
+ return NV_FALSE;
+ pmu->pfnAlarmInterrupt = func;
+ return NV_TRUE;
+}
+
+NvBool
+NvOdmPmuSuspendRtc(NvOdmPmuDeviceHandle hDevice)
+{
+ NvOdmPmuDevice *pmu = GetPmuInstance(hDevice);
+ if (pmu && pmu->pfnSuspendRtc)
+ return pmu->pfnSuspendRtc(pmu);
+ return NV_FALSE;
+}
+
+NvBool
+NvOdmPmuResumeRtc(NvOdmPmuDeviceHandle hDevice)
+{
+ NvOdmPmuDevice *pmu = GetPmuInstance(hDevice);
+ if (pmu && pmu->pfnResumeRtc)
+ return pmu->pfnResumeRtc(pmu);
+ return NV_FALSE;
+}