[ARM/tegra] add NvRm, ODM services, ODM kit for harmony & whistler

add power rail support to GPIO driver

Change-Id: I45d4c1110a635047d68fb14f3e72a28f99acbe1b

12 files changed, 3721 insertions, 0 deletions

diff --git a/arch/arm/mach-tegra/odm_kit/query/harmony/Makefile b/arch/arm/mach-tegra/odm_kit/query/harmony/Makefile
new file mode 100644
index 000000000000..bdc7cbfee77f
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/harmony/Makefile
@@ -0,0 +1,19 @@
+ccflags-y += -DNV_IS_AVP=0
+ccflags-y += -DNV_OAL=0
+ccflags-y += -DNV_USE_FUSE_CLOCK_ENABLE=0
+ifeq ($(CONFIG_MACH_TEGRA_GENERIC_DEBUG),y)
+ccflags-y += -DNV_DEBUG=1
+else
+ccflags-y += -DNV_DEBUG=0
+endif
+
+ccflags-y += -Iarch/arm/mach-tegra/odm_kit/adaptations
+ccflags-y += -Iarch/arm/mach-tegra/odm_kit/adaptations
+
+obj-y += nvodm_query.o
+obj-y += nvodm_query_discovery.o
+obj-y += nvodm_query_nand.o
+obj-y += nvodm_query_gpio.o
+obj-y += nvodm_query_pinmux.o
+obj-y += nvodm_query_kbc.o
+
diff --git a/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query.c b/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query.c
new file mode 100644
index 000000000000..62243eded55d
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query.c
@@ -0,0 +1,869 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA APX ODM Kit:
+ *         Implementation of the ODM Query API</b>
+ *
+ * @b Description: Implements the query functions for ODMs that may be
+ *                 accessed at boot-time, runtime, or anywhere in between.
+ */
+
+#include "nvodm_query.h"
+#include "nvodm_query_gpio.h"
+#include "nvodm_query_memc.h"
+#include "nvodm_query_discovery.h"
+#include "nvodm_query_pins.h"
+#include "nvodm_query_pins_ap20.h"
+#include "tegra_devkit_custopt.h"
+#include "nvodm_keylist_reserved.h"
+#include "nvrm_drf.h"
+
+#if !defined(NV_OAL)
+#define NV_OAL (0)
+#endif
+
+#define BOARD_ID_HARMONY 0x0B3E
+#define HARMONY_HYS5C1GB_SKU 0x3829
+
+#define NVODM_ENABLE_EMC_DVFS (1)
+
+// Although AP16 Concorde2 and AP16 Vail boards can support PMU
+// interrupt, keep it disabled for now because of PMU VBUS input
+// latch problem
+#define NVODM_PMU_INT_ENABLED (0)
+
+static const NvU8
+s_NvOdmQueryDeviceNamePrefixValue[] = {'T','e','g','r','a',0};
+
+static const NvU8
+s_NvOdmQueryManufacturerSetting[] = {'N','V','I','D','I','A',0};
+
+static const NvU8
+s_NvOdmQueryModelSetting[] = {'A','P','2','0',0};
+
+static const NvU8
+s_NvOdmQueryPlatformSetting[] = {'H','a','r','m','o','n','y',0};
+
+static const NvU8
+s_NvOdmQueryProjectNameSetting[] = {'O','D','M',' ','K','i','t',0};
+
+static const NvOdmDownloadTransport
+s_NvOdmQueryDownloadTransportSetting = NvOdmDownloadTransport_None;
+
+static const NvOdmQuerySdioInterfaceProperty s_NvOdmQuerySdioInterfaceProperty[4] =
+{
+    { NV_FALSE, 10,  NV_TRUE, 0x8, NvOdmQuerySdioSlotUsage_wlan   },
+    { NV_TRUE,   0, NV_FALSE, 0x5, NvOdmQuerySdioSlotUsage_Media  },
+    { NV_TRUE,   0, NV_FALSE, 0x6, NvOdmQuerySdioSlotUsage_unused },
+    { NV_TRUE,   0, NV_FALSE, 0x4, NvOdmQuerySdioSlotUsage_Media  }
+};
+
+static const NvOdmQuerySpiDeviceInfo s_NvOdmQuerySpiDeviceInfoTable [] =
+{
+    {NvOdmQuerySpiSignalMode_0, NV_TRUE}    // Spi1_Devices_0 (chip sel 0)
+};
+
+// Spi idle signal state
+static const NvOdmQuerySpiIdleSignalState s_NvOdmQuerySpiIdleSignalStateLevel[] =
+{
+    {NV_FALSE, NvOdmQuerySpiSignalMode_0, NV_FALSE}    // Spi 1
+};
+// We can have two I2s Instances
+static const NvOdmQueryI2sInterfaceProperty s_NvOdmQueryI2sInterfacePropertySetting[] =
+{
+    {
+        NvOdmQueryI2sMode_Master,               // Mode
+        NvOdmQueryI2sLRLineControl_LeftOnLow,   // I2sLRLineControl
+        NvOdmQueryI2sDataCommFormat_I2S,        // I2sDataCommunicationFormat
+        NV_FALSE,                               // IsFixedMCLK  
+        0                                       // FixedMCLKFrequency 
+    },
+    {
+        NvOdmQueryI2sMode_Master,               // Mode
+        NvOdmQueryI2sLRLineControl_LeftOnLow,   // I2sLRLineControl
+        NvOdmQueryI2sDataCommFormat_I2S,        // I2sDataCommunicationFormat
+        NV_FALSE,                               // IsFixedMCLK  
+        0                                       // FixedMCLKFrequency 
+    }
+};
+
+
+static const NvOdmQuerySpdifInterfaceProperty s_NvOdmQuerySpdifInterfacePropertySetting =
+{
+    NvOdmQuerySpdifDataCaptureControl_FromLeft
+};
+
+static const NvOdmQueryAc97InterfaceProperty s_NvOdmQueryAc97InterfacePropertySetting =
+{
+    NV_FALSE,
+    NV_FALSE,
+    NV_FALSE,
+    NV_FALSE,
+    NV_TRUE
+};
+
+// Add support for the Codec Formats
+// It must the order (dapIndex) how the codec is connected to the Dap port
+static const NvOdmQueryI2sACodecInterfaceProp s_NvOdmQueryI2sACodecInterfacePropSetting[] =
+{
+    {
+        NV_FALSE,                               // IsCodecMaster
+        0,                                      // DapPortIndex
+        0x36,                                   // DevAddress
+        NV_FALSE,                               // IsUsbmode
+        NvOdmQueryI2sLRLineControl_LeftOnLow,   // I2sCodecLRLineControl
+        NvOdmQueryI2sDataCommFormat_I2S         // I2sCodecDataCommFormat
+    }
+};
+
+static const NvOdmQueryDapPortConnection s_NvOdmQueryDapPortConnectionTable[] =
+{
+    // the Default Music Path
+    { NvOdmDapConnectionIndex_Music_Path, 2,
+    { {NvOdmDapPort_I2s1, NvOdmDapPort_Dap1, NV_TRUE},
+      {NvOdmDapPort_Dap1, NvOdmDapPort_I2s1, NV_FALSE}
+    }},
+
+    // Bluetooth to Codec
+    { NvOdmDapConnectionIndex_BlueTooth_Codec, 3,
+    { {NvOdmDapPort_Dap4, NvOdmDapPort_I2s1, NV_TRUE},
+      {NvOdmDapPort_I2s1, NvOdmDapPort_Dap4, NV_FALSE},
+      {NvOdmDapPort_I2s2, NvOdmDapPort_Dap1, NV_FALSE}
+    }}
+};
+
+
+// Ap20 support 5 dap ports
+// For port is connected to DAC(I2s) then PortMode is not valid- as Dac would be driving it
+static const NvOdmQueryDapPortProperty s_NvOdmQueryDapPortInfoTable[] =
+{
+    {NvOdmDapPort_None, NvOdmDapPort_None , {0, 0, 0, 0} }, // Reserved
+    // I2S1 (DAC1) <-> DAP1 <-> HIFICODEC
+    {NvOdmDapPort_I2s1, NvOdmDapPort_HifiCodecType,
+        {2, 16, 44100, NvOdmQueryI2sDataCommFormat_I2S}},   // Dap1
+    {NvOdmDapPort_None, NvOdmDapPort_None , {0, 0, 0, 0} }, // Dap2
+    {NvOdmDapPort_None, NvOdmDapPort_None , {0, 0, 0, 0} }, // Dap3
+    // I2S2 (DAC2) <-> DAP4 <-> BLUETOOTH
+    {NvOdmDapPort_I2s2, NvOdmDapPort_BlueTooth,
+        {2, 16, 8000, NvOdmQueryI2sDataCommFormat_I2S}}     // Dap4
+};
+
+static const NvOdmSdramControllerConfigAdv s_NvOdmHyS5c1GbEmcConfigTable[] =
+{
+    {
+                  0x20,   /* Rev 2.0 */
+                166500,   /* SDRAM frquency */
+                   950,   /* EMC core voltage */
+                    46,   /* Number of EMC parameters below */
+        {
+            0x0000000A,   /* RC */
+            0x00000016,   /* RFC */
+            0x00000008,   /* RAS */
+            0x00000003,   /* RP */
+            0x00000004,   /* R2W */
+            0x00000004,   /* W2R */
+            0x00000002,   /* R2P */
+            0x0000000C,   /* W2P */
+            0x00000003,   /* RD_RCD */
+            0x00000003,   /* WR_RCD */
+            0x00000002,   /* RRD */
+            0x00000001,   /* REXT */
+            0x00000004,   /* WDV */
+            0x00000005,   /* QUSE */
+            0x00000004,   /* QRST */
+            0x00000009,   /* QSAFE */
+            0x0000000D,   /* RDV */
+            0x000004DF,   /* REFRESH */
+            0x00000000,   /* BURST_REFRESH_NUM */
+            0x00000003,   /* PDEX2WR */
+            0x00000003,   /* PDEX2RD */
+            0x00000003,   /* PCHG2PDEN */
+            0x00000003,   /* ACT2PDEN */
+            0x00000001,   /* AR2PDEN */
+            0x0000000A,   /* RW2PDEN */
+            0x000000C8,   /* TXSR */
+            0x00000003,   /* TCKE */
+            0x00000006,   /* TFAW */
+            0x00000004,   /* TRPAB */
+            0x00000008,   /* TCLKSTABLE */
+            0x00000002,   /* TCLKSTOP */
+            0x00000000,   /* TREFBW */
+            0x00000000,   /* QUSE_EXTRA */
+            0x00000002,   /* FBIO_CFG6 */
+            0x00000000,   /* ODT_WRITE */
+            0x00000000,   /* ODT_READ */
+            0x00000083,   /* FBIO_CFG5 */
+            0xE03B0323,   /* CFG_DIG_DLL */
+            0x007FC010,   /* DLL_XFORM_DQS */
+            0x00008010,   /* DLL_XFORM_QUSE */
+            0x00000000,   /* ZCAL_REF_CNT */
+            0x00000000,   /* ZCAL_WAIT_CNT */
+            0x00000000,   /* AUTO_CAL_INTERVAL */
+            0x00000000,   /* CFG_CLKTRIM_0 */
+            0x00000000,   /* CFG_CLKTRIM_1 */
+            0x00000000,   /* CFG_CLKTRIM_2 */
+        }
+    },
+    {
+                  0x20,   /* Rev 2.0 */
+                333000,   /* SDRAM frquency */
+                  1200,   /* EMC core voltage */
+                    46,   /* Number of EMC parameters below */
+        {
+            0x00000014,   /* RC */
+            0x0000002B,   /* RFC */
+            0x0000000F,   /* RAS */
+            0x00000005,   /* RP */
+            0x00000004,   /* R2W */
+            0x00000005,   /* W2R */
+            0x00000003,   /* R2P */
+            0x0000000C,   /* W2P */
+            0x00000005,   /* RD_RCD */
+            0x00000005,   /* WR_RCD */
+            0x00000003,   /* RRD */
+            0x00000001,   /* REXT */
+            0x00000004,   /* WDV */
+            0x00000005,   /* QUSE */
+            0x00000004,   /* QRST */
+            0x00000009,   /* QSAFE */
+            0x0000000D,   /* RDV */
+            0x000009FF,   /* REFRESH */
+            0x00000000,   /* BURST_REFRESH_NUM */
+            0x00000003,   /* PDEX2WR */
+            0x00000003,   /* PDEX2RD */
+            0x00000005,   /* PCHG2PDEN */
+            0x00000005,   /* ACT2PDEN */
+            0x00000001,   /* AR2PDEN */
+            0x0000000F,   /* RW2PDEN */
+            0x000000C8,   /* TXSR */
+            0x00000003,   /* TCKE */
+            0x0000000C,   /* TFAW */
+            0x00000006,   /* TRPAB */
+            0x00000008,   /* TCLKSTABLE */
+            0x00000002,   /* TCLKSTOP */
+            0x00000000,   /* TREFBW */
+            0x00000000,   /* QUSE_EXTRA */
+            0x00000002,   /* FBIO_CFG6 */
+            0x00000000,   /* ODT_WRITE */
+            0x00000000,   /* ODT_READ */
+            0x00000083,   /* FBIO_CFG5 */
+            0xF0320303,   /* CFG_DIG_DLL */
+            0x007FC010,   /* DLL_XFORM_DQS */
+            0x00008010,   /* DLL_XFORM_QUSE */
+            0x00000000,   /* ZCAL_REF_CNT */
+            0x00000000,   /* ZCAL_WAIT_CNT */
+            0x00000000,   /* AUTO_CAL_INTERVAL */
+            0x00000000,   /* CFG_CLKTRIM_0 */
+            0x00000000,   /* CFG_CLKTRIM_1 */
+            0x00000000,   /* CFG_CLKTRIM_2 */
+        }
+    }
+};
+
+// Wake Events
+static NvOdmWakeupPadInfo s_NvOdmWakeupPadInfo[] =
+{
+    {NV_FALSE,  0, NvOdmWakeupPadPolarity_Low},     // Wake Event  0 - ulpi_data4 (UART_RI)
+    {NV_FALSE,  1, NvOdmWakeupPadPolarity_High},    // Wake Event  1 - gp3_pv[3] (BB_MOD, MODEM_RESET_OUT)
+    {NV_FALSE,  2, NvOdmWakeupPadPolarity_High},    // Wake Event  2 - dvi_d3
+    {NV_FALSE,  3, NvOdmWakeupPadPolarity_Low},     // Wake Event  3 - sdio3_dat1
+    {NV_FALSE,  4, NvOdmWakeupPadPolarity_High},    // Wake Event  4 - hdmi_int (HDMI_HPD)
+    {NV_TRUE,   5, NvOdmWakeupPadPolarity_Low},     // Wake Event  5 - vgp[6] (VI_GP6, Flash_EN2)
+    {NV_FALSE,  6, NvOdmWakeupPadPolarity_High},    // Wake Event  6 - gp3_pu[5] (GPS_ON_OFF, GPS_IRQ)
+    {NV_FALSE,  7, NvOdmWakeupPadPolarity_AnyEdge}, // Wake Event  7 - gp3_pu[6] (GPS_INT, BT_IRQ)
+    {NV_FALSE,  8, NvOdmWakeupPadPolarity_AnyEdge}, // Wake Event  8 - gmi_wp_n (MICRO SD_CD)
+    {NV_FALSE,  9, NvOdmWakeupPadPolarity_High},    // Wake Event  9 - gp3_ps[2] (KB_COL10)
+    {NV_FALSE, 10, NvOdmWakeupPadPolarity_High},    // Wake Event 10 - gmi_ad21 (Accelerometer_TH/TAP)
+    {NV_TRUE,  11, NvOdmWakeupPadPolarity_Low},     // Wake Event 11 - spi2_cs2 (PEN_INT, AUDIO-IRQ, LOW_BAT#)
+    {NV_FALSE, 12, NvOdmWakeupPadPolarity_Low},     // Wake Event 12 - spi2_cs1 (HEADSET_DET, not used)
+    {NV_FALSE, 13, NvOdmWakeupPadPolarity_Low},     // Wake Event 13 - sdio1_dat1
+    {NV_FALSE, 14, NvOdmWakeupPadPolarity_High},    // Wake Event 14 - gp3_pv[6] (WLAN_INT)
+    {NV_FALSE, 15, NvOdmWakeupPadPolarity_AnyEdge}, // Wake Event 15 - gmi_ad16  (SPI3_DOUT, DTV_SPI4_CS1)
+    {NV_TRUE,  16, NvOdmWakeupPadPolarity_High},    // Wake Event 16 - rtc_irq
+#ifdef CONFIG_KEYBOARD_TEGRA
+    {NV_TRUE,  17, NvOdmWakeupPadPolarity_High},    // Wake Event 17 - kbc_interrupt
+#else
+    {NV_FALSE, 17, NvOdmWakeupPadPolarity_High},
+#endif
+    {NV_FALSE, 18, NvOdmWakeupPadPolarity_Low},     // Wake Event 18 - pwr_int (PMIC_INT)
+    {NV_FALSE, 19, NvOdmWakeupPadPolarity_AnyEdge}, // Wake Event 19 - usb_vbus_wakeup[0]
+    {NV_FALSE, 20, NvOdmWakeupPadPolarity_High},    // Wake Event 20 - usb_vbus_wakeup[1]
+    {NV_FALSE, 21, NvOdmWakeupPadPolarity_Low},     // Wake Event 21 - usb_iddig[0]
+    {NV_FALSE, 22, NvOdmWakeupPadPolarity_Low},     // Wake Event 22 - usb_iddig[1]
+    {NV_TRUE,  23, NvOdmWakeupPadPolarity_AnyEdge}, // Wake Event 23 - gmi_iordy (HSMMC_CLK)
+    {NV_FALSE, 24, NvOdmWakeupPadPolarity_High},    // Wake Event 24 - gp3_pv[2] (BB_MOD, MODEM WAKEUP_AP15, SPI-SS)
+    {NV_FALSE, 25, NvOdmWakeupPadPolarity_High},    // Wake Event 25 - gp3_ps[4] (KB_COL12)
+    {NV_FALSE, 26, NvOdmWakeupPadPolarity_High},    // Wake Event 26 - gp3_ps[5] (KB_COL10)
+    {NV_FALSE, 27, NvOdmWakeupPadPolarity_High},    // Wake Event 27 - gp3_ps[0] (KB_COL8)
+    {NV_FALSE, 28, NvOdmWakeupPadPolarity_Low},     // Wake Event 28 - gp3_pq[6] (KB_ROW6)
+    {NV_FALSE, 29, NvOdmWakeupPadPolarity_Low},     // Wake Event 29 - gp3_pq[7] (KB_ROW6)
+    {NV_FALSE, 30, NvOdmWakeupPadPolarity_High}     // Wake Event 30 - dap1_dout (DAP1_DOUT)
+};
+
+/* --- Function Implementations ---*/
+static NvU32
+GetBctKeyValue(void)
+{
+    NvOdmServicesKeyListHandle hKeyList = NULL;
+    NvU32 BctCustOpt = 0;
+
+    hKeyList = NvOdmServicesKeyListOpen();
+    if (hKeyList)
+    {
+        BctCustOpt =
+            NvOdmServicesGetKeyValue(hKeyList,
+                                     NvOdmKeyListId_ReservedBctCustomerOption);
+        NvOdmServicesKeyListClose(hKeyList);
+    }
+
+    return BctCustOpt;
+}
+
+NvOdmDebugConsole
+NvOdmQueryDebugConsole(void)
+{
+    NvU32 CustOpt = GetBctKeyValue();
+    switch (NV_DRF_VAL(TEGRA_DEVKIT, BCT_CUSTOPT, CONSOLE, CustOpt))
+    {
+    case TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_DEFAULT:
+    case TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_DCC:
+        return NvOdmDebugConsole_Dcc;
+    case TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_NONE:
+        return NvOdmDebugConsole_None;
+    case TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_UART:
+        return NvOdmDebugConsole_UartA +
+            NV_DRF_VAL(TEGRA_DEVKIT, BCT_CUSTOPT, CONSOLE_OPTION, CustOpt);
+    default:
+        return NvOdmDebugConsole_None;
+    }
+}
+
+NvOdmDownloadTransport
+NvOdmQueryDownloadTransport(void)
+{
+    NvU32 CustOpt = GetBctKeyValue();
+
+    switch (NV_DRF_VAL(TEGRA_DEVKIT, BCT_CUSTOPT, TRANSPORT, CustOpt))
+    {
+    case TEGRA_DEVKIT_BCT_CUSTOPT_0_TRANSPORT_NONE:
+        return NvOdmDownloadTransport_None;
+    case TEGRA_DEVKIT_BCT_CUSTOPT_0_TRANSPORT_USB:
+        return NvOdmDownloadTransport_Usb;
+    case TEGRA_DEVKIT_BCT_CUSTOPT_0_TRANSPORT_ETHERNET:
+        switch (NV_DRF_VAL(TEGRA_DEVKIT, BCT_CUSTOPT, ETHERNET_OPTION, CustOpt))
+        {
+        case TEGRA_DEVKIT_BCT_CUSTOPT_0_ETHERNET_OPTION_SPI:
+        case TEGRA_DEVKIT_BCT_CUSTOPT_0_ETHERNET_OPTION_DEFAULT:
+        default:
+            return NvOdmDownloadTransport_SpiEthernet;
+        }
+    case TEGRA_DEVKIT_BCT_CUSTOPT_0_TRANSPORT_UART:
+        switch (NV_DRF_VAL(TEGRA_DEVKIT, BCT_CUSTOPT, UART_OPTION, CustOpt))
+        {
+        case TEGRA_DEVKIT_BCT_CUSTOPT_0_UART_OPTION_B:
+            return NvOdmDownloadTransport_UartB;
+        case TEGRA_DEVKIT_BCT_CUSTOPT_0_UART_OPTION_C:
+            return NvOdmDownloadTransport_UartC;
+        case TEGRA_DEVKIT_BCT_CUSTOPT_0_UART_OPTION_DEFAULT:
+        case TEGRA_DEVKIT_BCT_CUSTOPT_0_UART_OPTION_A:
+        default:
+            return NvOdmDownloadTransport_UartA;
+        }
+    case TEGRA_DEVKIT_BCT_CUSTOPT_0_TRANSPORT_DEFAULT:
+    default:
+        return s_NvOdmQueryDownloadTransportSetting;
+    }
+}
+
+const NvU8*
+NvOdmQueryDeviceNamePrefix(void)
+{
+    return s_NvOdmQueryDeviceNamePrefixValue;
+}
+
+const NvOdmQuerySpiDeviceInfo *
+NvOdmQuerySpiGetDeviceInfo(
+    NvOdmIoModule OdmIoModule,
+    NvU32 ControllerId,
+    NvU32 ChipSelect)
+{
+    if (OdmIoModule == NvOdmIoModule_Spi)
+    {
+        switch (ControllerId)
+        {
+            case 0:
+                if (ChipSelect == 0)
+                    return &s_NvOdmQuerySpiDeviceInfoTable[0];
+                break;
+
+            default:
+                break;
+        }
+        return NULL;
+    }
+    return NULL;
+}
+
+const NvOdmQuerySpiIdleSignalState *
+NvOdmQuerySpiGetIdleSignalState(
+    NvOdmIoModule OdmIoModule,
+    NvU32 ControllerId)
+{
+    if (OdmIoModule == NvOdmIoModule_Spi)
+    {
+        if (ControllerId == 0)
+            return &s_NvOdmQuerySpiIdleSignalStateLevel[0];
+    }
+    return NULL;
+}
+
+const NvOdmQueryI2sInterfaceProperty *
+NvOdmQueryI2sGetInterfaceProperty(
+    NvU32 I2sInstanceId)
+{
+    if ((I2sInstanceId == 0) || (I2sInstanceId == 1))
+        return &s_NvOdmQueryI2sInterfacePropertySetting[I2sInstanceId];
+
+    return NULL;
+}
+
+const NvOdmQueryDapPortProperty *
+NvOdmQueryDapPortGetProperty(
+    NvU32 DapPortId)
+{
+    if (DapPortId > 0 && DapPortId < NV_ARRAY_SIZE(s_NvOdmQueryDapPortInfoTable) )
+        return &s_NvOdmQueryDapPortInfoTable[DapPortId];
+
+    return NULL;
+}
+
+const NvOdmQueryDapPortConnection*
+NvOdmQueryDapPortGetConnectionTable(
+    NvU32 ConnectionIndex)
+{
+    NvU32 TableIndex   = 0;
+    for( TableIndex = 0; 
+         TableIndex < NV_ARRAY_SIZE(s_NvOdmQueryDapPortConnectionTable);
+         TableIndex++)
+    {
+        if (s_NvOdmQueryDapPortConnectionTable[TableIndex].UseIndex 
+                                                    == ConnectionIndex)
+            return &s_NvOdmQueryDapPortConnectionTable[TableIndex];
+    }
+    return NULL;
+}
+
+const NvOdmQuerySpdifInterfaceProperty *
+NvOdmQuerySpdifGetInterfaceProperty(
+    NvU32 SpdifInstanceId)
+{
+    if (SpdifInstanceId == 0)
+        return &s_NvOdmQuerySpdifInterfacePropertySetting;
+
+    return NULL;
+}
+
+const NvOdmQueryAc97InterfaceProperty *
+NvOdmQueryAc97GetInterfaceProperty(
+    NvU32 Ac97InstanceId)
+{
+    if (Ac97InstanceId == 0)
+        return &s_NvOdmQueryAc97InterfacePropertySetting;
+
+    return NULL;
+}
+
+const NvOdmQueryI2sACodecInterfaceProp *
+NvOdmQueryGetI2sACodecInterfaceProperty(
+    NvU32 AudioCodecId)
+{
+    NvU32 NumInstance = sizeof(s_NvOdmQueryI2sACodecInterfacePropSetting)/
+                            sizeof(s_NvOdmQueryI2sACodecInterfacePropSetting[0]);
+    if (AudioCodecId < NumInstance)
+        return &s_NvOdmQueryI2sACodecInterfacePropSetting[AudioCodecId];
+
+    return NULL;
+}
+
+/**
+ * This function is called from early boot process.
+ * Therefore, it cannot use global variables.
+ */
+NvBool NvOdmQueryAsynchMemConfig(
+    NvU32 ChipSelect,
+    NvOdmAsynchMemConfig *pMemConfig)
+{
+    return NV_FALSE;
+}
+
+const void*
+NvOdmQuerySdramControllerConfigGet(NvU32 *pEntries, NvU32 *pRevision)
+{
+#if NVODM_ENABLE_EMC_DVFS
+    NvOdmBoardInfo BoardInfo;
+
+    if (NvOdmPeripheralGetBoardInfo(BOARD_ID_HARMONY, &BoardInfo))
+    {
+        if (BoardInfo.SKU == HARMONY_HYS5C1GB_SKU)
+        {
+            if (pRevision)
+                *pRevision = s_NvOdmHyS5c1GbEmcConfigTable[0].Revision;
+            if (pEntries)
+                *pEntries = NV_ARRAY_SIZE(s_NvOdmHyS5c1GbEmcConfigTable);
+            return (const void*)s_NvOdmHyS5c1GbEmcConfigTable;
+        }
+    }
+#endif
+    if (pEntries)
+        *pEntries = 0;
+    return NULL;
+}
+
+NvOdmQueryOscillator NvOdmQueryGetOscillatorSource(void)
+{
+    return NvOdmQueryOscillator_Xtal;
+}
+
+NvU32 NvOdmQueryGetOscillatorDriveStrength(void)
+{
+    /// Oscillator drive strength range is 0 to 0x3F
+    return 0x04;
+}
+
+const NvOdmWakeupPadInfo *NvOdmQueryGetWakeupPadTable(NvU32 *pSize)
+{
+    if (pSize)
+        *pSize = NV_ARRAY_SIZE(s_NvOdmWakeupPadInfo);
+
+    return (const NvOdmWakeupPadInfo *) s_NvOdmWakeupPadInfo;
+}
+
+const NvU8* NvOdmQueryManufacturer(void)
+{
+    return s_NvOdmQueryManufacturerSetting;
+}
+
+const NvU8* NvOdmQueryModel(void)
+{
+    return s_NvOdmQueryModelSetting;
+}
+
+const NvU8* NvOdmQueryPlatform(void)
+{
+    return s_NvOdmQueryPlatformSetting;
+}
+
+const NvU8* NvOdmQueryProjectName(void)
+{
+    return s_NvOdmQueryProjectNameSetting;
+}
+
+#define EXT 0     // external pull-up/down resistor
+#define INT_PU 1  // internal pull-up
+#define INT_PD 2  // internal pull-down
+
+#define HIGHSPEED 1
+#define SCHMITT 1
+#define VREF    1
+#define OHM_50 3
+#define OHM_100 2
+#define OHM_200 1
+#define OHM_400 0
+
+ // Pin attributes
+static const NvOdmPinAttrib pin_config[] = {
+    // Pull ups for the kbc pins
+    { NvOdmPinRegister_Ap20_PullUpDown_B,
+     NVODM_QUERY_PIN_AP20_PULLUPDOWN_B(0x0, 0x0, 0x0, 0x0, 0x2, 0x2, 0x2, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0) },
+
+    // Pull ups for the kbc pins
+    { NvOdmPinRegister_Ap20_PullUpDown_E,
+     NVODM_QUERY_PIN_AP20_PULLUPDOWN_E(0x2, 0x2, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0, 0x2, 0x2) },
+
+    // Set pad control for the sdio2 - - AOCFG1 and AOCFG2 pad control register
+    { NvOdmPinRegister_Ap20_PadCtrl_AOCFG1PADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_50, 31, 31, 3, 3) },
+
+    { NvOdmPinRegister_Ap20_PadCtrl_AOCFG2PADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_50, 31, 31, 3, 3) },
+
+    // Set pad control for the sdio3 - SDIO2 and SDIO3 pad control register
+    { NvOdmPinRegister_Ap20_PadCtrl_SDIO2CFGPADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_50, 31, 31, 3, 3) },
+
+    { NvOdmPinRegister_Ap20_PadCtrl_SDIO3CFGPADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_50, 31, 31, 3, 3) },
+
+    // Set pad control for I2C1 pins
+    { NvOdmPinRegister_Ap20_PadCtrl_DBGCFGPADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_50, 31, 31, 3, 3) },
+
+    { NvOdmPinRegister_Ap20_PadCtrl_VICFG1PADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_50, 31, 31, 3, 3) },
+
+    { NvOdmPinRegister_Ap20_PadCtrl_VICFG2PADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_50, 31, 31, 3, 3) },
+
+    // Set pad control for I2C2 (DDC) pins
+    { NvOdmPinRegister_Ap20_PadCtrl_DDCCFGPADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_50, 31, 31, 3, 3) },
+
+    // Set pad control for the sdio1 - SDIO1 pad control register
+    { NvOdmPinRegister_Ap20_PadCtrl_SDIO1CFGPADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_50, 31, 31, 3, 3) },
+
+     // WiFi Pins (DTA, DTD) need to be pulled up
+    { NvOdmPinRegister_Ap20_PullUpDown_A,
+      NVODM_QUERY_PIN_AP20_PULLUPDOWN_A(0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0, 0x0, 0x2, 0x0, 0x0, 0x0) },
+
+    // Set pad control for the sdio4- ATCCFG1 and ATCCFG2 pad control register
+    { NvOdmPinRegister_Ap20_PadCtrl_ATCFG1PADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_50, 31, 31, 3, 3) },
+
+    { NvOdmPinRegister_Ap20_PadCtrl_ATCFG2PADCTRL,
+      NVODM_QUERY_PIN_AP20_PADCTRL_AOCFG1PADCTRL(!HIGHSPEED, SCHMITT, OHM_50, 31, 31, 3, 3) }
+};
+
+NvU32
+NvOdmQueryPinAttributes(const NvOdmPinAttrib** pPinAttributes)
+{
+    if (pPinAttributes)
+    {
+        *pPinAttributes = &pin_config[0];
+        return NV_ARRAY_SIZE(pin_config);
+    }
+    return 0;
+}
+
+NvBool NvOdmQueryGetPmuProperty(NvOdmPmuProperty* pPmuProperty)
+{
+    pPmuProperty->IrqConnected = NV_FALSE;
+    pPmuProperty->PowerGoodCount = 0x7E;
+    pPmuProperty->IrqPolarity = NvOdmInterruptPolarity_Low;
+    pPmuProperty->CorePowerReqPolarity = NvOdmCorePowerReqPolarity_Low;
+    pPmuProperty->SysClockReqPolarity = NvOdmSysClockReqPolarity_High;
+    pPmuProperty->CombinedPowerReq = NV_FALSE;
+    pPmuProperty->CpuPowerGoodUs = 2000;
+    pPmuProperty->AccuracyPercent = 3;
+    pPmuProperty->VCpuOTPOnWakeup = NV_FALSE;
+    return NV_TRUE;
+}
+
+/**
+ * Gets the lowest soc power state supported by the hardware
+ *
+ * @returns information about the SocPowerState
+ */
+const NvOdmSocPowerStateInfo* NvOdmQueryLowestSocPowerState(void)
+{
+
+    static                      NvOdmSocPowerStateInfo  PowerStateInfo;
+    const static                NvOdmSocPowerStateInfo* pPowerStateInfo = NULL;
+    NvOdmServicesKeyListHandle  hKeyList;
+    NvU32                       LPStateSelection = 0;
+    if (pPowerStateInfo == NULL)
+    {
+
+        hKeyList = NvOdmServicesKeyListOpen();
+        if (hKeyList)
+        {
+            LPStateSelection = NvOdmServicesGetKeyValue(hKeyList,
+                                                NvOdmKeyListId_ReservedBctCustomerOption);
+            NvOdmServicesKeyListClose(hKeyList);
+            LPStateSelection = NV_DRF_VAL(TEGRA_DEVKIT, BCT_CUSTOPT, LPSTATE, LPStateSelection);
+        }
+        // Lowest power state controlled by the flashed custom option.
+        PowerStateInfo.LowestPowerState =  ((LPStateSelection != TEGRA_DEVKIT_BCT_CUSTOPT_0_LPSTATE_LP1)?
+                                            NvOdmSocPowerState_Suspend : NvOdmSocPowerState_DeepSleep);
+        pPowerStateInfo = (const NvOdmSocPowerStateInfo*) &PowerStateInfo;
+    }
+    return (pPowerStateInfo);
+}
+
+const NvOdmUsbProperty*
+NvOdmQueryGetUsbProperty(NvOdmIoModule OdmIoModule,
+                         NvU32 Instance)
+{
+    static const NvOdmUsbProperty Usb1Property =
+    {
+        NvOdmUsbInterfaceType_Utmi,
+        (NvOdmUsbChargerType_SE0 | NvOdmUsbChargerType_SE1 | NvOdmUsbChargerType_SK),
+        20,
+        NV_TRUE,
+        NvOdmUsbModeType_Device,
+        NvOdmUsbIdPinType_CableId,
+        NvOdmUsbConnectorsMuxType_None,
+        NV_TRUE
+    };
+
+     static const NvOdmUsbProperty Usb2Property =
+     {
+        NvOdmUsbInterfaceType_UlpiExternalPhy,
+        NvOdmUsbChargerType_UsbHost,
+        20,
+        NV_TRUE,
+        NvOdmUsbModeType_Host,
+        NvOdmUsbIdPinType_None,
+        NvOdmUsbConnectorsMuxType_None,
+        NV_TRUE
+    };
+
+    static const NvOdmUsbProperty Usb3Property =
+    {
+        NvOdmUsbInterfaceType_Utmi,
+        NvOdmUsbChargerType_UsbHost,
+        20,
+        NV_TRUE,
+        NvOdmUsbModeType_Host,
+        NvOdmUsbIdPinType_None,
+        NvOdmUsbConnectorsMuxType_None,
+        NV_TRUE
+    };
+
+    if (OdmIoModule == NvOdmIoModule_Usb && Instance == 0)
+        return &(Usb1Property);
+
+    if (OdmIoModule == NvOdmIoModule_Usb && Instance == 1)
+        return &(Usb2Property);
+
+    if (OdmIoModule == NvOdmIoModule_Usb && Instance == 2)
+        return &(Usb3Property);
+
+    return (const NvOdmUsbProperty *)NULL;
+}
+
+const NvOdmQuerySdioInterfaceProperty* NvOdmQueryGetSdioInterfaceProperty(NvU32 Instance)
+{
+    return &s_NvOdmQuerySdioInterfaceProperty[Instance];
+}
+
+const NvOdmQueryHsmmcInterfaceProperty* NvOdmQueryGetHsmmcInterfaceProperty(NvU32 Instance)
+{
+    return NULL;
+}
+
+NvU32
+NvOdmQueryGetBlockDeviceSectorSize(NvOdmIoModule OdmIoModule)
+{
+    return 0;
+}
+
+const NvOdmQueryOwrDeviceInfo* NvOdmQueryGetOwrDeviceInfo(NvU32 Instance)
+{
+    return NULL;
+}
+
+const NvOdmGpioWakeupSource *NvOdmQueryGetWakeupSources(NvU32 *pCount)
+{
+    *pCount = 0;
+    return NULL;
+}
+
+/**
+ * This function is called from early boot process.
+ * Therefore, it cannot use global variables.
+ */
+NvU32 NvOdmQueryMemSize(NvOdmMemoryType MemType)
+{
+    NvOdmOsOsInfo Info;
+    NvU32 MemBctCustOpt = GetBctKeyValue();
+
+    switch (MemType)
+    {
+        // NOTE:
+        // For Windows CE/WM operating systems the total size of SDRAM may
+        // need to be reduced due to limitations in the virtual address map.
+        // Under the legacy physical memory manager, Windows OSs have a
+        // maximum 512MB statically mapped virtual address space. Under the
+        // new physical memory manager, Windows OSs have a maximum 1GB
+        // statically mapped virtual address space. Out of that virtual
+        // address space, the upper 32 or 36 MB (depending upon the SOC)
+        // of the virtual address space is reserved for SOC register
+        // apertures.
+        //
+        // Refer to virtual_tables_apxx.arm for the reserved aperture list.
+        // If the cumulative size of the reserved apertures changes, the
+        // maximum size of SDRAM will also change.
+        case NvOdmMemoryType_Sdram:
+            switch (NV_DRF_VAL(TEGRA_DEVKIT, BCT_SYSTEM, MEMORY, MemBctCustOpt))
+            {
+                case TEGRA_DEVKIT_BCT_SYSTEM_0_MEMORY_256:
+                    if ( NvOdmOsGetOsInformation(&Info) &&
+                         ((Info.OsType!=NvOdmOsOs_Windows) ||
+                          (Info.OsType==NvOdmOsOs_Windows && Info.MajorVersion>=7)) )
+                        return 0x10000000;
+                    else
+                        return 0x0DD00000;  // Legacy Physical Memory Manager: 256 MB - 35 MB
+    
+                case TEGRA_DEVKIT_BCT_SYSTEM_0_MEMORY_1024:
+                    if ( NvOdmOsGetOsInformation(&Info) &&
+                         ((Info.OsType!=NvOdmOsOs_Windows) ||
+                          (Info.OsType==NvOdmOsOs_Windows && Info.MajorVersion>=7)) )
+                        return 0x40000000;
+                    else
+                        // Earlier versions of WinCE only support 512MB max memory size
+                        return 0x1E000000;  // Legacy Physical Memory Manager: 512 MB - 32 MB
+
+                case TEGRA_DEVKIT_BCT_SYSTEM_0_MEMORY_512:
+                case TEGRA_DEVKIT_BCT_SYSTEM_0_MEMORY_DEFAULT:
+                default:
+                    if ( NvOdmOsGetOsInformation(&Info) &&
+                         ((Info.OsType!=NvOdmOsOs_Windows) ||
+                          (Info.OsType==NvOdmOsOs_Windows && Info.MajorVersion>=7)) )
+                        return 0x20000000;
+                    else
+                        return 0x1E000000;  // Legacy Physical Memory Manager: 512 MB - 32 MB
+            }
+
+        case NvOdmMemoryType_Nor:
+            return 0x00400000;  // 4 MB
+
+        case NvOdmMemoryType_Nand:
+        case NvOdmMemoryType_I2CEeprom:
+        case NvOdmMemoryType_Hsmmc:
+        case NvOdmMemoryType_Mio:
+        default:
+            return 0;
+    }
+}
+
+NvU32 NvOdmQueryCarveoutSize(void)
+{
+    return 0x04000000;  // 64 MB
+}
+
+NvU32 NvOdmQuerySecureRegionSize(void)
+{
+    return 0x00800000;// 8 MB
+}
diff --git a/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query_discovery.c b/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query_discovery.c
new file mode 100644
index 000000000000..6b0b896d0cf3
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query_discovery.c
@@ -0,0 +1,770 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA APX ODM Kit::
+ *         Implementation of the ODM Peripheral Discovery API</b>
+ *
+ * @b Description: The peripheral connectivity database implementation.
+ */
+
+#include "nvcommon.h"
+#include "nvodm_query_gpio.h"
+#include "nvodm_modules.h"
+#include "nvodm_query_discovery.h"
+#include "nvodm_keylist_reserved.h"
+#include "tegra_devkit_custopt.h"
+#include "nvodm_query.h"
+#include "nvrm_drf.h"
+
+#include "subboards/nvodm_query_discovery_e1162_addresses.h"
+
+static NvOdmPeripheralConnectivity s_Peripherals_Default[] =
+{
+#include "subboards/nvodm_query_discovery_e1162_peripherals.h"
+};
+
+#define NVODM_QUERY_BOARD_ID_UNKNOWN    0xFFFF
+
+#define NVODM_QUERY_MAX_PERIPHERALS     0x400
+#define NVODM_QUERY_MAX_IO_ADDRESSES    0x400
+
+#define NVODM_QUERY_MAX_EEPROMS         8   // Maximum number of EEPROMs per bus segment
+
+#define NVODM_QUERY_ERASED_EEPROM_VALUE 0xFF
+
+#define PROCESSOR_BOARD_ID_I2C_ADDRESS ((0x56)<<1)
+#define PROCESSOR_BOARD_ID_I2C_SEGMENT (0x00)
+
+// The following are used to store entries read from EEPROMs at runtime.
+static NvOdmPeripheralConnectivity s_Peripherals[NVODM_QUERY_MAX_PERIPHERALS];
+static NvOdmIoAddress s_Peripheral_IoAddresses[NVODM_QUERY_MAX_IO_ADDRESSES];
+static NvOdmBoardInfo s_BoardModuleTable[NVODM_QUERY_MAX_EEPROMS];
+
+#define NVODM_QUERY_I2C_CLOCK_SPEED      100    // kHz
+
+#define NVODM_QUERY_ENTRY_HEADER_SIZE    0x30   // Size of EERPOM "Entry Header"
+#define NVODM_QUERY_BOARD_HEADER_START   0x04   // Offset to Part Number in EERPOM
+
+#define NVODM_QUERY_I2C_EEPROM_ADDRESS   0xA0   // I2C device base address for EEPROM (7'h50)
+
+#define NVODM_QUERY_PERIPH_CONN_STRUCT_COMPRESSED   10  // See EEPROM_format.txt
+#define NVODM_PERIPH_IO_ADDR_STRUCT_SZ_COMPRESSED   2   // See EEPROM_format.txt
+
+
+static NvOdmI2cStatus
+NvOdmPeripheralI2cRead8(
+    NvOdmServicesI2cHandle hOdmI2c,
+    NvU8 I2cAddr,
+    NvU8 Offset,
+    NvU8 *pData)
+{
+    NvU8 ReadBuffer[1];
+    NvOdmI2cStatus Error;    
+    NvOdmI2cTransactionInfo TransactionInfo;
+
+    ReadBuffer[0] = Offset;
+
+    TransactionInfo.Address = I2cAddr;
+    TransactionInfo.Buf = ReadBuffer;
+    TransactionInfo.Flags = NVODM_I2C_IS_WRITE;
+    TransactionInfo.NumBytes = 1;
+
+    Error = NvOdmI2cTransaction(
+        hOdmI2c, &TransactionInfo, 1, NVODM_QUERY_I2C_CLOCK_SPEED, NV_WAIT_INFINITE);
+    if (Error != NvOdmI2cStatus_Success)
+    {
+        return Error;
+    }
+
+    NvOdmOsMemset(ReadBuffer, 0, sizeof(ReadBuffer));  
+
+    TransactionInfo.Address = (I2cAddr | 0x1);
+    TransactionInfo.Buf = ReadBuffer;
+    TransactionInfo.Flags = 0;
+    TransactionInfo.NumBytes = 1;
+
+    // Read data from ROM at the specified offset
+    Error = NvOdmI2cTransaction(
+        hOdmI2c, &TransactionInfo, 1, NVODM_QUERY_I2C_CLOCK_SPEED, NV_WAIT_INFINITE);
+    if (Error != NvOdmI2cStatus_Success)
+    {
+        return Error;
+    }
+    *pData = ReadBuffer[0];
+    return Error;
+}
+
+static NvBool
+NvOdmPeripheralReadNumPeripherals(
+    NvOdmServicesI2cHandle hOdmI2c,
+    NvU8 EepromInst,
+    NvU8 *pNumModulePeripherals)
+{
+    NvOdmI2cStatus Error;    
+    NvU8 I2cAddr, Offset;
+
+    // EepromInst*2, since 7-bit addressing
+    I2cAddr = NVODM_QUERY_I2C_EEPROM_ADDRESS + (EepromInst << 1);
+
+    /**
+     * Offset to numPeripherals in NvOdmPeripheralConnectivity Structure.
+     * It's the first parameter after the "Entry Header."
+     */
+    Offset = NVODM_QUERY_ENTRY_HEADER_SIZE;
+
+    Error = NvOdmPeripheralI2cRead8(
+        hOdmI2c, I2cAddr, Offset, pNumModulePeripherals);
+    if (Error != NvOdmI2cStatus_Success)
+    {
+        return NV_FALSE;
+    }
+    return NV_TRUE;
+}
+
+static NvBool
+NvOdmPeripheralReadPeripheral(
+    NvOdmServicesI2cHandle hOdmI2c,
+    NvU8 EepromInst,
+    NvU8 Peripheral,
+    NvU64 *pGuid,
+    NvU8 *pEepromAddressListOffset,
+    NvU32 *pNumAddress,
+    NvOdmPeripheralClass *pClass)
+{
+    NvOdmI2cStatus Error;    
+    NvU32 i;
+    NvU8 ConnMemberIndex=0; // Offset to members in NvOdmPeripheralConnectivity
+    NvU8 I2cAddr, Offset;
+    NvU8 ReadBuffer[NVODM_QUERY_PERIPH_CONN_STRUCT_COMPRESSED];
+    NvU8 NumAddrAndClass;
+
+    // EepromInst*2, since 7-bit addressing
+    I2cAddr = NVODM_QUERY_I2C_EEPROM_ADDRESS + (EepromInst << 1);
+
+    /**
+     * Calculate offset to pGuid in NvOdmPeripheralConnectivity Structure
+     * 
+     *  Offset = sizeof(eeprom Entry Header) + 
+     *           sizeof(NvOdmPeripheralConnectivity)*peripheral + 
+     *           pGuid offset    <-- First field, so this is 0
+     */
+    Offset = NVODM_QUERY_ENTRY_HEADER_SIZE + 
+        sizeof(NvOdmPeripheralConnectivity)*Peripheral;
+
+    for (i=0; i<NVODM_QUERY_PERIPH_CONN_STRUCT_COMPRESSED; i++)
+    {
+        Error = NvOdmPeripheralI2cRead8(
+            hOdmI2c, I2cAddr, Offset, (NvU8 *)&ReadBuffer[i]);
+        if (Error != NvOdmI2cStatus_Success)
+        {
+            return NV_FALSE;
+        }
+    }
+    // Save pGuid entry
+    NvOdmOsMemcpy(pGuid, &ReadBuffer[0], sizeof(NvU64));
+
+    // Save EEPROM offset
+    ConnMemberIndex += sizeof(NvU64); // Increment to next member
+    *pEepromAddressListOffset = ReadBuffer[ConnMemberIndex];
+
+    // Save pNumAddress & Class
+    ConnMemberIndex += sizeof(NvU8); // Increment to next member
+    NumAddrAndClass = ReadBuffer[ConnMemberIndex];
+    *pNumAddress = (NvU32)((NumAddrAndClass >> 3) & 0x0000001F);
+    *pClass = (NvOdmPeripheralClass)(NumAddrAndClass & 0x00000007);
+
+    return NV_TRUE;
+}
+
+static NvBool
+NvOdmPeripheralReadIoAddressData(
+    NvOdmServicesI2cHandle hOdmI2c,
+    NvU8 EepromInst,
+    NvU8 EepromAddressListOffset,
+    NvOdmIoAddress *pIoAddressEntry)
+{
+    NvOdmI2cStatus Error;    
+    NvU32 i;
+    NvU8 I2cAddr;
+    NvU8 ReadBuffer[NVODM_PERIPH_IO_ADDR_STRUCT_SZ_COMPRESSED];
+    NvU16 CompressedIoAddressEntry;
+
+    // EepromInst*2, since 7-bit addressing
+    I2cAddr = NVODM_QUERY_I2C_EEPROM_ADDRESS + (EepromInst << 1);
+
+    for (i=0; i<NVODM_PERIPH_IO_ADDR_STRUCT_SZ_COMPRESSED; i++)
+    {
+        Error = NvOdmPeripheralI2cRead8(
+            hOdmI2c, I2cAddr, EepromAddressListOffset, (NvU8 *)&ReadBuffer[i]);
+        if (Error != NvOdmI2cStatus_Success)
+        {
+            return NV_FALSE;
+        }
+    }
+    // Save pIoAddressEntry: interface, instance, address
+    CompressedIoAddressEntry = ((((NvU16)ReadBuffer[1]) << 8) & 0xFF00) | ReadBuffer[0];
+
+    pIoAddressEntry->Interface = (NvOdmIoModule)((CompressedIoAddressEntry >> 11) & 0x1F);
+
+    if (pIoAddressEntry->Interface != NvOdmIoModule_Gpio)
+    {
+        pIoAddressEntry->Instance = (NvU32)((CompressedIoAddressEntry >> 7) & 0xF);
+        pIoAddressEntry->Address = (NvU32)(CompressedIoAddressEntry & 0x7F);
+    }
+    else
+    {
+        pIoAddressEntry->Address = (NvU32)((CompressedIoAddressEntry >> 6) & 0x3F);
+        pIoAddressEntry->Instance = (NvU32)(CompressedIoAddressEntry & 0x3F);
+    }
+
+    return NV_TRUE;
+}
+
+static NvBool NvOdmPeripheralGetEntries(NvU32 *pNum)
+{
+    NvBool RetVal;
+    NvBool IsMatch = NV_FALSE;
+    NvOdmServicesI2cHandle hOdmI2c = NULL;
+    NvU8 EepromInst;
+
+    // Peripheral counters
+    NvU8 NumPeripherals = 0;
+    NvU8 CurrentPeripheral = 0;
+    NvU32 TotalPeripherals = 0;
+    NvU32 StaticPeripherals;
+
+    NvU32 CurrentIoAddressNum = 0;
+    NvU32 TotalIoAddressEntries = 0;
+
+    NvU32 i,j;
+    NvU8 EepromAddressListOffset;
+
+    if (!pNum) {
+        return NV_FALSE;
+    }
+
+    // Auto-detect -- Read I2C-EEPROMs on each sub-board
+
+    hOdmI2c = NvOdmI2cOpen(NvOdmIoModule_I2c_Pmu, 0);
+    if (!hOdmI2c)
+        return NV_FALSE;
+
+    for (EepromInst=0; EepromInst < NVODM_QUERY_MAX_EEPROMS; EepromInst++)
+    {
+        RetVal = NvOdmPeripheralReadNumPeripherals(
+            hOdmI2c, EepromInst, &NumPeripherals);
+
+        if ( (RetVal == NV_TRUE) &&
+             (NumPeripherals != NVODM_QUERY_ERASED_EEPROM_VALUE) )
+        {
+            if (NumPeripherals > 0)
+            {
+                if ((NumPeripherals + TotalPeripherals) > NVODM_QUERY_MAX_PERIPHERALS)
+                {
+                    NV_ASSERT( !"ERROR: s_Peripherals[] is too small to accommodate entries!" );
+
+                    // Break out of loop and use static/default configuration
+                    break;
+                }
+
+                for (CurrentPeripheral=0; \
+                      CurrentPeripheral < NumPeripherals; \
+                      CurrentPeripheral++)
+                {
+                    RetVal = NvOdmPeripheralReadPeripheral(
+                        hOdmI2c,
+                        EepromInst,
+                        CurrentPeripheral,
+                        &s_Peripherals[TotalPeripherals+CurrentPeripheral].Guid,
+                        &EepromAddressListOffset,
+                        &s_Peripherals[TotalPeripherals+CurrentPeripheral].NumAddress,
+                        &s_Peripherals[TotalPeripherals+CurrentPeripheral].Class);
+
+                    if (RetVal == NV_FALSE)
+                    {
+                        NV_ASSERT(!"Unable to read EEPROM peripheral entry!");
+                        break;  // Go to next EEPROM
+                    }
+                    else // Process peripheral entry
+                    {
+                        /**
+                         * Process NvOdmIoAddress arrays --
+                         * 
+                         * These are separate data structures.  The addressList value
+                         * read from the EEPROM (EepromAddressListOffset) represents
+                         * an offset address within the I2C-EEPROM.  This offset value
+                         * identifies where to find the first instance of the
+                         * NvOdmIoAddress data.
+                         * 
+                         * The total number of NvOdmIoAddress entries is identified
+                         * by the numAddress variable following the addressList entry
+                         * in EEPROM.
+                         * 
+                         * Once the offset and number of entries are determined (from
+                         * above NvOdmPeripheralReadPeripheral function call), a loop
+                         * fills in entries within the fixed storage area
+                         * (e.g., s_Peripheral_IoAddresses) and the actual
+                         * addressList pointer is assigned a value that corresponds
+                         * to the first entry of the current class within this array.
+                         * In other words, there might be prior entries in the
+                         * s_Peripheral_IoAddresses array, but the first entry
+                         * corresponding to the current class might be the third
+                         * element in this array.  Therefore, the actual addressList
+                         * pointer for the current NvOdmPeripheralConnectivity.addressList
+                         * parameter would be the address of the third entry, which is
+                         * &s_Peripheral_IoAddresses[2] in this example.
+                         */
+
+                        // Read all of the entries and save them in s_Peripheral_IoAddresses
+                        for (CurrentIoAddressNum=0; \
+                              CurrentIoAddressNum < s_Peripherals[TotalPeripherals+CurrentPeripheral].NumAddress; \
+                              CurrentIoAddressNum++)
+                        {
+                            if (TotalIoAddressEntries > NVODM_QUERY_MAX_IO_ADDRESSES)
+                            {
+                                NV_ASSERT( !"ERROR: s_Peripheral_IoAddresses[] is too small to accommodate entries!" );
+
+                                // Cannot recover from this error.
+                                NvOdmI2cClose(hOdmI2c);
+                                return NV_FALSE;
+                            }
+
+                            RetVal = NvOdmPeripheralReadIoAddressData(
+                                hOdmI2c,
+                                EepromInst,
+                                EepromAddressListOffset,
+                                &s_Peripheral_IoAddresses[TotalIoAddressEntries+CurrentIoAddressNum]);
+
+                            if (RetVal == NV_FALSE)
+                            {
+                                NV_ASSERT(!"Unable to read EEPROM (IoAddresses)!");
+
+                                // Cannot recover from this error.
+                                NvOdmI2cClose(hOdmI2c);
+                                return NV_FALSE;
+                            }
+                            else // Process IoAddresses entry
+                            {
+                                /**
+                                 * Save the addressList pointer. This points to the first 
+                                 * IoAddresses entry of this class.  Then update the overall 
+                                 * IoAddresses array counter (TotalIoAddressEntries).
+                                 */
+                                s_Peripherals[TotalPeripherals+CurrentPeripheral].AddressList = 
+                                    &s_Peripheral_IoAddresses[TotalIoAddressEntries];
+
+                                TotalIoAddressEntries += CurrentIoAddressNum;
+
+                                // >-- End of NvOdmIoAddress array processing --<
+                            }
+                        }
+                    }
+                }
+            }
+            TotalPeripherals += NumPeripherals;
+        }
+    }
+
+    // Done reading I2C-EEPROM; close it.
+    NvOdmI2cClose(hOdmI2c);
+
+    /** 
+     *  Append static peripheral entries (if any) to dynamic list
+     *  read from EEPROMs (this list may also be empty), except for
+     *  duplicate GUIDs.  The dynamic list takes precedence when
+     *  duplicate entries are found in the static list.
+     */
+    StaticPeripherals = NV_ARRAY_SIZE(s_Peripherals_Default);
+    for (i=0; i<StaticPeripherals; i++)
+    {
+        for (j=0; j<TotalPeripherals; j++)
+        {
+            if (s_Peripherals_Default[i].Guid == s_Peripherals[j].Guid)
+            {
+                IsMatch = NV_TRUE;
+                break;  // Ignore duplicate entry from static list.
+            }
+        }
+        if (IsMatch != NV_TRUE)
+        {
+            // Append unique entry to dynamic list
+
+            s_Peripherals[TotalPeripherals].Guid = 
+                s_Peripherals_Default[i].Guid;
+
+            s_Peripherals[TotalPeripherals].AddressList = 
+                s_Peripherals_Default[i].AddressList;
+
+            s_Peripherals[TotalPeripherals].NumAddress = 
+                s_Peripherals_Default[i].NumAddress;
+
+            s_Peripherals[TotalPeripherals].Class = 
+                s_Peripherals_Default[i].Class;
+
+            TotalPeripherals++;
+        }
+    }
+    *pNum = TotalPeripherals;
+    return NV_TRUE;
+}
+
+static NvBool
+NvOdmPeripheralReadPartNumber(
+    NvOdmServicesI2cHandle hOdmI2c,
+    NvU8 EepromInst,
+    NvOdmBoardInfo *pBoardInfo)
+{
+    NvOdmI2cStatus Error;
+    NvU32 i;
+    NvU8 I2cAddr, Offset;
+    NvU8 ReadBuffer[sizeof(NvOdmBoardInfo)];
+
+    NvOdmOsMemset(ReadBuffer, 0, sizeof(ReadBuffer));  
+
+    // EepromInst*2, since 7-bit addressing
+    I2cAddr = NVODM_QUERY_I2C_EEPROM_ADDRESS + (EepromInst << 1);
+
+    /**
+     * Offset to the board number entry in EEPROM.
+     */
+    Offset = NVODM_QUERY_BOARD_HEADER_START;
+
+    for (i=0; i<sizeof(NvOdmBoardInfo); i++)
+    {
+        Error = NvOdmPeripheralI2cRead8(
+            hOdmI2c, I2cAddr, Offset+i, (NvU8 *)&ReadBuffer[i]);
+        if (Error != NvOdmI2cStatus_Success)
+        {
+            return NV_FALSE;
+        }
+    }
+    NvOdmOsMemcpy(pBoardInfo, &ReadBuffer[0], sizeof(NvOdmBoardInfo));
+    return NV_TRUE;
+}
+
+NvBool
+NvOdmPeripheralGetBoardInfo(
+    NvU16 BoardId,
+    NvOdmBoardInfo *pBoardInfo)
+{
+    NvBool RetVal = NV_FALSE;
+    NvOdmServicesI2cHandle hOdmI2c = NULL;
+    NvU8 EepromInst, CurrentBoard;
+    static NvU8 NumBoards = 0;
+    static NvBool s_ReadBoardInfoDone = NV_FALSE;
+
+    if (!s_ReadBoardInfoDone)
+    {
+        s_ReadBoardInfoDone = NV_TRUE;
+        hOdmI2c = NvOdmI2cOpen(NvOdmIoModule_I2c_Pmu, 0);
+        if (!hOdmI2c)
+        {
+            // Exit
+            pBoardInfo = NULL;
+            return NV_FALSE;
+        }
+
+        for (EepromInst=0; EepromInst < NVODM_QUERY_MAX_EEPROMS; EepromInst++)
+        {
+            RetVal = NvOdmPeripheralReadPartNumber(
+                    hOdmI2c, EepromInst, &s_BoardModuleTable[NumBoards]);
+            if (RetVal == NV_TRUE)
+                NumBoards++;
+        }
+        NvOdmI2cClose(hOdmI2c);
+    }
+
+    if (NumBoards)
+    {
+        // Linear search for given BoardId; if found, return entry
+        for (CurrentBoard=0; CurrentBoard < NumBoards; CurrentBoard++)
+        {
+            if (s_BoardModuleTable[CurrentBoard].BoardID == BoardId)
+            {
+                // Match found
+                pBoardInfo->BoardID  = s_BoardModuleTable[CurrentBoard].BoardID;
+                pBoardInfo->SKU      = s_BoardModuleTable[CurrentBoard].SKU;
+                pBoardInfo->Fab      = s_BoardModuleTable[CurrentBoard].Fab;
+                pBoardInfo->Revision = s_BoardModuleTable[CurrentBoard].Revision;
+                pBoardInfo->MinorRevision = s_BoardModuleTable[CurrentBoard].MinorRevision;
+                return NV_TRUE;
+            }           
+        }
+    }
+
+    // Match not found
+    pBoardInfo = NULL;
+    return NV_FALSE;
+}
+
+// This will compare the peripheral GUID against a list of known-bad GUIDs
+// for certain development kit personalities, and return NV_TRUE if it is
+// known to be unsupported (filtered) on the current configuration
+static NvBool
+NvIsFilteredPeripheral(const NvOdmPeripheralConnectivity* pConnectivity)
+{
+    NvOdmServicesKeyListHandle hKeyList;
+    NvU32 Personality = 0;
+    NvU32 opt = 0;
+    NvOdmIoModule OdmModule;
+    const NvU32 *OdmConfigs=NULL;
+    NvU32 NumOdmConfigs = 0;
+    const NvOdmPeripheralConnectivity* pFilteredPeriph = pConnectivity;
+
+    if((!pConnectivity) || (!pConnectivity->NumAddress))
+        return NV_TRUE;
+
+    hKeyList = NvOdmServicesKeyListOpen();
+
+    if (hKeyList)
+    {
+        Personality =
+            NvOdmServicesGetKeyValue(hKeyList,
+                                     NvOdmKeyListId_ReservedBctCustomerOption);
+        NvOdmServicesKeyListClose(hKeyList);
+        Personality = 
+            NV_DRF_VAL(TEGRA_DEVKIT, BCT_CUSTOPT, PERSONALITY, Personality);
+        opt =
+            NV_DRF_VAL(TEGRA_DEVKIT, BCT_CUSTOPT, DISPLAY_OPTION, opt);
+    }
+
+    if (!Personality)
+        Personality = TEGRA_DEVKIT_DEFAULT_PERSONALITY;
+
+    OdmModule = pFilteredPeriph->AddressList[0].Interface;
+
+    if(OdmModule != NvOdmIoModule_Gpio)
+        NvOdmQueryPinMux(OdmModule, &OdmConfigs, &NumOdmConfigs);
+
+    switch (OdmModule)
+    {
+    case NvOdmIoModule_Gpio:
+        // Filter scroll wheel when trace is enabled
+        if ( (pConnectivity->Guid == NV_ODM_GUID('s','c','r','o','l','w','h','l')) &&
+             ((Personality == TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_11) ||
+              (Personality == TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_15) ||
+              (Personality == TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_C1)) )
+            return NV_TRUE;
+        else
+            return NV_FALSE;
+
+    default:
+        return NV_FALSE;
+    }
+}
+
+static const NvOdmPeripheralConnectivity* 
+NvApGetAllPeripherals (NvU32 *pNum)
+{
+    static NvBool s_AutoDetectDone = NV_FALSE;
+    NvBool RetVal = NV_TRUE;
+    static NvU32 s_TotalPeripherals;
+    NvOdmBoardInfo BoardInfo;
+
+    if (!pNum)
+        return NULL;
+
+    if (!s_AutoDetectDone)
+    {
+        /**
+         *  Read & cache the board ID info from the I2C-EEPROMs.  This
+         *  is necessary because once Whistler's thermal power rail is
+         *  enabled, the ID ROMs cannot be read. NvApGetAllPeripherals()
+         *  is called before that rail is enabled.
+         */
+        NvOdmPeripheralGetBoardInfo(NVODM_QUERY_BOARD_ID_UNKNOWN, &BoardInfo);
+
+        RetVal = NvOdmPeripheralGetEntries(&s_TotalPeripherals);
+        if (RetVal == NV_FALSE)
+        {
+            *pNum = 0;
+            return NULL;
+        }
+        s_AutoDetectDone = NV_TRUE;
+    }
+
+    *pNum = s_TotalPeripherals;
+    return (const NvOdmPeripheralConnectivity *)s_Peripherals;
+}
+
+// This implements a simple linear search across the entire set of currently-
+// connected peripherals to find the set of GUIDs that Match the search
+// criteria.  More clever implementations are possible, but given the
+// relatively small search space (max dozens of peripherals) and the relative
+// infrequency of enumerating peripherals, this is the easiest implementation.
+const NvOdmPeripheralConnectivity *
+NvOdmPeripheralGetGuid(NvU64 SearchGuid)
+{
+    const NvOdmPeripheralConnectivity *pAllPeripherals;
+    NvU32 NumPeripherals;
+    NvU32 i;
+
+    pAllPeripherals = NvApGetAllPeripherals(&NumPeripherals);
+
+    if (!pAllPeripherals || !NumPeripherals)
+        return NULL;
+
+    for (i=0; i<NumPeripherals; i++) 
+    {
+        if (SearchGuid == pAllPeripherals[i].Guid)
+        {
+            if (NvIsFilteredPeripheral(&pAllPeripherals[i]))
+                return NULL;
+            return &pAllPeripherals[i];
+        }
+    }
+
+    return NULL;
+}
+
+static NvBool
+IsBusMatch(
+    const NvOdmPeripheralConnectivity *pPeriph,
+    const NvOdmPeripheralSearch *pSearchAttrs,
+    const NvU32 *pSearchVals,
+    NvU32 offset,
+    NvU32 NumAttrs)
+{
+    NvU32 i, j;
+    NvBool IsMatch = NV_FALSE;
+
+    for (i=0; i<pPeriph->NumAddress; i++)
+    {
+        j = offset;
+        do
+        {
+            switch (pSearchAttrs[j])
+            {
+            case NvOdmPeripheralSearch_IoModule:
+                IsMatch = (pSearchVals[j] ==
+                           (NvU32)(pPeriph->AddressList[i].Interface));
+                break;
+            case NvOdmPeripheralSearch_Address:
+                IsMatch = (pSearchVals[j] == pPeriph->AddressList[i].Address);
+                break;
+            case NvOdmPeripheralSearch_Instance:
+                IsMatch = (pSearchVals[j] == pPeriph->AddressList[i].Instance);
+                break;
+            case NvOdmPeripheralSearch_PeripheralClass:
+            default:
+                NV_ASSERT(!"Bad Query!");
+                break;
+            }
+            j++;
+        } while (IsMatch && j<NumAttrs &&
+                 pSearchAttrs[j]!=NvOdmPeripheralSearch_IoModule);
+
+        if (IsMatch)
+        {
+            return NV_TRUE;
+        }
+    }
+    return NV_FALSE;
+}
+
+static NvBool
+IsPeripheralMatch(
+    const NvOdmPeripheralConnectivity *pPeriph,
+    const NvOdmPeripheralSearch *pSearchAttrs,
+    const NvU32 *pSearchVals,
+    NvU32 NumAttrs)
+{
+    NvU32 i;
+    NvBool IsMatch = NV_TRUE;
+
+    for (i=0; i<NumAttrs && IsMatch; i++)
+    {
+        switch (pSearchAttrs[i])
+        {
+        case NvOdmPeripheralSearch_PeripheralClass:
+            IsMatch = (pSearchVals[i] == (NvU32)(pPeriph->Class));
+            break;
+        case NvOdmPeripheralSearch_IoModule:
+            IsMatch = IsBusMatch(pPeriph, pSearchAttrs, pSearchVals, i, NumAttrs);
+            break;
+        case NvOdmPeripheralSearch_Address:
+        case NvOdmPeripheralSearch_Instance:
+            // In correctly-formed searches, these parameters will be parsed by
+            // IsBusMatch, so we ignore them here.
+            break;
+        default:
+            NV_ASSERT(!"Bad search attribute!");
+            break;
+        }
+    }
+    return IsMatch;
+}
+
+NvU32
+NvOdmPeripheralEnumerate(
+    const NvOdmPeripheralSearch *pSearchAttrs,
+    const NvU32 *pSearchVals,
+    NvU32 NumAttrs,
+    NvU64 *pGuidList,
+    NvU32 NumGuids)
+{
+    const NvOdmPeripheralConnectivity *pAllPeripherals;
+    NvU32 NumPeripherals;
+    NvU32 Matches;
+    NvU32 i;
+
+    pAllPeripherals = NvApGetAllPeripherals(&NumPeripherals);
+
+    if (!pAllPeripherals || !NumPeripherals)
+    {
+        return 0;
+    }
+
+    if (!pSearchAttrs || !pSearchVals)
+    {
+        NumAttrs = 0;
+    }
+    for (i=0, Matches=0; i<NumPeripherals &&
+             (Matches < NumGuids || !pGuidList); i++)
+    {
+        if ( !NumAttrs || IsPeripheralMatch(&pAllPeripherals[i],
+                                            pSearchAttrs, pSearchVals,
+                                            NumAttrs) )
+        {
+            if (NvIsFilteredPeripheral(&pAllPeripherals[i]))
+                continue;
+
+            if (pGuidList)
+                pGuidList[Matches] = pAllPeripherals[i].Guid;
+            Matches++;
+        }
+    }
+    return Matches;
+}
+
diff --git a/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query_gpio.c b/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query_gpio.c
new file mode 100644
index 000000000000..8d384db176ee
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query_gpio.c
@@ -0,0 +1,240 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "nvodm_query_gpio.h"
+#include "nvodm_services.h"
+#include "nvrm_drf.h"
+
+#define NVODM_ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+#define NVODM_PORT(x) ((x) - 'a')
+
+static const NvOdmGpioPinInfo s_vi[] = {
+    {NVODM_PORT('t'), 3, NvOdmGpioPinActiveState_High}, // EN_VDDIO_SD
+};
+
+static const NvOdmGpioPinInfo s_display[] = {
+
+    // TO DO: Verify these settings for harmony.
+
+    /* Panel 0 -- sony vga */
+    { NVODM_PORT('m'), 3, NvOdmGpioPinActiveState_Low },
+    { NVODM_PORT('b'), 2, NvOdmGpioPinActiveState_Low },
+    { NVODM_PORT('n'), 4, NvOdmGpioPinActiveState_Low },
+    { NVODM_PORT('j'), 3, NvOdmGpioPinActiveState_Low },
+    { NVODM_PORT('j'), 4, NvOdmGpioPinActiveState_Low },
+    // this pin is not needed for ap15
+    {NVODM_GPIO_INVALID_PORT, NVODM_GPIO_INVALID_PIN,
+        NvOdmGpioPinActiveState_Low},
+
+    /* Panel 1 -- samtek */
+    {NVODM_GPIO_INVALID_PORT, NVODM_GPIO_INVALID_PIN,
+        NvOdmGpioPinActiveState_Low},
+    {NVODM_GPIO_INVALID_PORT, NVODM_GPIO_INVALID_PIN,
+        NvOdmGpioPinActiveState_Low},
+    {NVODM_GPIO_INVALID_PORT, NVODM_GPIO_INVALID_PIN,
+        NvOdmGpioPinActiveState_Low},
+    {NVODM_GPIO_INVALID_PORT, NVODM_GPIO_INVALID_PIN,
+        NvOdmGpioPinActiveState_Low},
+
+    /* Panel 2 -- sharp wvga */
+    { NVODM_PORT('v'), 7, NvOdmGpioPinActiveState_Low },
+
+    /* Panel 3 -- sharp qvga */
+    { NVODM_PORT('n'), 6, NvOdmGpioPinActiveState_High },   // LCD_DC0
+    { NVODM_PORT('n'), 4, NvOdmGpioPinActiveState_Low },    // LCD_CS0
+    { NVODM_PORT('b'), 3, NvOdmGpioPinActiveState_Low },    // LCD_PCLK
+    { NVODM_PORT('b'), 2, NvOdmGpioPinActiveState_Low },    // LCD_PWR0
+    { NVODM_PORT('e'), 0, NvOdmGpioPinActiveState_High },   // LCD_D0
+    { NVODM_PORT('e'), 1, NvOdmGpioPinActiveState_High },   // LCD_D1
+    { NVODM_PORT('e'), 2, NvOdmGpioPinActiveState_High },   // LCD_D2
+    { NVODM_PORT('e'), 3, NvOdmGpioPinActiveState_High },   // LCD_D3
+    { NVODM_PORT('e'), 4, NvOdmGpioPinActiveState_High },   // LCD_D4
+    { NVODM_PORT('e'), 5, NvOdmGpioPinActiveState_High },   // LCD_D5
+    { NVODM_PORT('e'), 6, NvOdmGpioPinActiveState_High },   // LCD_D6
+    { NVODM_PORT('e'), 7, NvOdmGpioPinActiveState_High },   // LCD_D7
+    { NVODM_PORT('f'), 0, NvOdmGpioPinActiveState_High },   // LCD_D8
+    { NVODM_PORT('f'), 1, NvOdmGpioPinActiveState_High },   // LCD_D9
+    { NVODM_PORT('f'), 2, NvOdmGpioPinActiveState_High },   // LCD_D10
+    { NVODM_PORT('f'), 3, NvOdmGpioPinActiveState_High },   // LCD_D11
+    { NVODM_PORT('f'), 4, NvOdmGpioPinActiveState_High },   // LCD_D12
+    { NVODM_PORT('f'), 5, NvOdmGpioPinActiveState_High },   // LCD_D13
+    { NVODM_PORT('f'), 6, NvOdmGpioPinActiveState_High },   // LCD_D14
+    { NVODM_PORT('f'), 7, NvOdmGpioPinActiveState_High },   // LCD_D15
+    { NVODM_PORT('m'), 3, NvOdmGpioPinActiveState_High },   // LCD_D19
+
+    /* Panel 4 -- auo */
+    { NVODM_PORT('v'), 7, NvOdmGpioPinActiveState_Low },
+
+    /* Panel 5 -- firefly p1138 lvds interface */
+    {NVODM_GPIO_INVALID_PORT, NVODM_GPIO_INVALID_PIN, NvOdmGpioPinActiveState_Low},
+    { NVODM_PORT('b'), 4, NvOdmGpioPinActiveState_High },   // LCD_BL_PWM
+    { NVODM_PORT('b'), 5, NvOdmGpioPinActiveState_High },   // LCD_BL_EN
+    { NVODM_PORT('c'), 6, NvOdmGpioPinActiveState_High },   // EN_VDD_PNL
+};
+
+static const NvOdmGpioPinInfo s_hdmi[] =
+{
+    /* hdmi hot-plug interrupt pin */
+    { NVODM_PORT('n'), 7, NvOdmGpioPinActiveState_High },    // HDMI HPD
+};
+
+static const NvOdmGpioPinInfo s_crt[] =
+{
+    /* crt hot-plug interrupt pin */
+    { NVODM_PORT('x'), 2, NvOdmGpioPinActiveState_Low }, // VGA_DET#
+};
+
+static const NvOdmGpioPinInfo s_sdio[] = {
+    {NVODM_PORT('i'), 5, NvOdmGpioPinActiveState_Low},    // Card Detect for SDIO instance 2
+    /* High for WP and low for read/write */
+    {NVODM_PORT('h'), 1, NvOdmGpioPinActiveState_High},    // Write Protect for SDIO instance 2 
+};
+
+static const NvOdmGpioPinInfo s_sdio3[] = {
+    {NVODM_PORT('h'), 2, NvOdmGpioPinActiveState_Low},    // Card Detect for SDIO instance 3
+    /* High for WP and low for read/write */
+    {NVODM_PORT('h'), 3, NvOdmGpioPinActiveState_High},    // Write Protect for SDIO instance 3
+};
+
+static const NvOdmGpioPinInfo s_NandFlash[] = {
+    {NVODM_PORT('c'), 7, NvOdmGpioPinActiveState_High}, // Raw NAND WP_N
+};
+
+static const NvOdmGpioPinInfo s_spi_ethernet[] = {
+    {NVODM_PORT('c'), 1, NvOdmGpioPinActiveState_Low}   // DBG_IRQ
+};
+
+static const NvOdmGpioPinInfo s_Bluetooth[] = {
+    {NVODM_PORT('u'), 0, NvOdmGpioPinActiveState_Low}   // BT_RST#
+};
+
+static const NvOdmGpioPinInfo s_Wlan[] = {
+    {NVODM_PORT('k'), 5, NvOdmGpioPinActiveState_Low},  // WF_PWDN#
+    {NVODM_PORT('k'), 6, NvOdmGpioPinActiveState_Low}   // WF_RST#
+};
+
+static const NvOdmGpioPinInfo s_Power[] = {
+    // lid open/close, High = Lid Closed
+    {NVODM_PORT('u'), 5, NvOdmGpioPinActiveState_High},
+    // power button
+    {NVODM_PORT('v'), 2, NvOdmGpioPinActiveState_Low}
+};
+
+static const NvOdmGpioPinInfo s_WakeFromKeyBoard[] = {
+    {NVODM_PORT('a'), 0, NvOdmGpioPinActiveState_Low}   // EC Keyboard Wakeup
+};
+
+static const NvOdmGpioPinInfo s_Battery[] = {
+    // Low Battery
+    {NVODM_PORT('w'), 3, NvOdmGpioPinActiveState_Low},
+};
+
+const NvOdmGpioPinInfo *NvOdmQueryGpioPinMap(NvOdmGpioPinGroup Group,
+    NvU32 Instance, NvU32 *pCount)
+{
+    switch (Group)
+    {
+        case NvOdmGpioPinGroup_Display:
+            *pCount = NVODM_ARRAY_SIZE(s_display);
+            return s_display;
+
+        case NvOdmGpioPinGroup_Hdmi:
+            *pCount = NVODM_ARRAY_SIZE(s_hdmi);
+            return s_hdmi;
+
+        case NvOdmGpioPinGroup_Crt:
+            *pCount = NVODM_ARRAY_SIZE(s_crt);
+            return s_crt;
+
+        case NvOdmGpioPinGroup_Sdio:
+            if (Instance == 1)
+            {
+                *pCount = NVODM_ARRAY_SIZE(s_sdio);
+                return s_sdio;
+            }
+            else if (Instance == 3)
+            {
+                *pCount = NVODM_ARRAY_SIZE(s_sdio3);
+                return s_sdio3;
+            }
+            else
+            {
+                *pCount = 0;
+                return NULL;
+            }
+
+        case NvOdmGpioPinGroup_NandFlash:
+            *pCount = NVODM_ARRAY_SIZE(s_NandFlash);
+            return s_NandFlash;
+
+        case NvOdmGpioPinGroup_Bluetooth:
+            *pCount = NVODM_ARRAY_SIZE(s_Bluetooth);
+            return s_Bluetooth;
+
+        case NvOdmGpioPinGroup_Wlan:
+            *pCount = NVODM_ARRAY_SIZE(s_Wlan);
+            return s_Wlan;
+
+        case NvOdmGpioPinGroup_SpiEthernet:
+            if (NvOdmQueryDownloadTransport() ==
+                NvOdmDownloadTransport_SpiEthernet)
+            {
+                *pCount = NVODM_ARRAY_SIZE(s_spi_ethernet);
+                return s_spi_ethernet;
+            }
+            else
+            {
+                *pCount = 0;
+                return NULL;
+            }
+        
+        case NvOdmGpioPinGroup_Vi:
+            *pCount = NVODM_ARRAY_SIZE(s_vi);
+            return s_vi;
+
+        case NvOdmGpioPinGroup_Power:
+            *pCount = NVODM_ARRAY_SIZE(s_Power);
+            return s_Power;
+
+        case NvOdmGpioPinGroup_WakeFromECKeyboard:
+            *pCount = NVODM_ARRAY_SIZE(s_WakeFromKeyBoard);
+            return s_WakeFromKeyBoard;
+
+        case NvOdmGpioPinGroup_Battery:
+            *pCount = NVODM_ARRAY_SIZE(s_Battery);
+            return s_Battery;
+
+        default:
+            *pCount = 0;
+            return NULL;
+    }
+}
diff --git a/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query_kbc.c b/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query_kbc.c
new file mode 100644
index 000000000000..951fc9730f41
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query_kbc.c
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * @brief <b>NVIDIA Driver Development Kit:
+ *                  ODM Kbc interface</b>
+ *
+ */
+
+#include "nvodm_query_kbc.h"
+#include "nvodm_query_kbc_gpio_def.h"
+#include "nvodm_query_kbc_qwerty_def.h"
+
+static NvU32 RowNumbers[] = {1, 15};
+static NvU32 ColNumbers[] = {7, 0};
+
+void
+NvOdmKbcGetParameter(
+        NvOdmKbcParameter Param,
+        NvU32 SizeOfValue,
+        void * pValue)
+{
+    NvU32 *pTempVar;
+    switch (Param)
+    {
+        case NvOdmKbcParameter_DebounceTime:
+            pTempVar = (NvU32 *)pValue;
+            *pTempVar = 2;
+            break;
+        case NvOdmKbcParameter_RepeatCycleTime:
+            pTempVar = (NvU32 *)pValue;
+            *pTempVar = 5;
+            break;
+        default:
+            break;
+    }
+}
+
+NvU32 
+NvOdmKbcGetKeyCode(
+    NvU32 Row, 
+    NvU32 Column,
+    NvU32 RowCount,
+    NvU32 ColumnCount)
+{
+    NvU32 CodeData;
+    if (Row < KBC_QWERTY_FUNCTION_KEY_ROW_BASE)
+    {
+        CodeData = KBC_QWERTY_NORMAL_KEY_CODE_BASE + ((Row * ColumnCount) + Column);
+    }    
+    else
+    {
+        CodeData = KBC_QWERTY_FUNCTION_KEY_CODE_BASE + 
+                        (((Row - KBC_QWERTY_FUNCTION_KEY_ROW_BASE) * ColumnCount) + Column);
+    }
+    return CodeData;
+}
+
+NvBool
+NvOdmKbcIsSelectKeysWkUpEnabled(
+    NvU32 **pRowNumber,
+    NvU32 **pColNumber,
+    NvU32 *NumOfKeys)
+{
+    *pRowNumber = &RowNumbers[0];
+    *pColNumber = &ColNumbers[0];
+    *NumOfKeys = 2;
+    return NV_TRUE;
+}
+
diff --git a/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query_kbc_gpio_def.h b/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query_kbc_gpio_def.h
new file mode 100644
index 000000000000..2e625eb6217d
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query_kbc_gpio_def.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA APX ODM Kit::
+ *         The KBC GPIO pin definitions</b>
+ *
+ * @b Description: Define the KBC GPIO pins in row and column numbers.
+ */
+
+#ifndef NVODM_QUERY_KBC_GPIO_DEF_H
+#define NVODM_QUERY_KBC_GPIO_DEF_H
+
+typedef enum
+{
+    NvOdmKbcGpioPin_KBRow0 = 0,
+    NvOdmKbcGpioPin_KBRow1,
+    NvOdmKbcGpioPin_KBRow2,
+    NvOdmKbcGpioPin_KBRow3,
+    NvOdmKbcGpioPin_KBRow4,
+    NvOdmKbcGpioPin_KBRow5,
+    NvOdmKbcGpioPin_KBRow6,
+    NvOdmKbcGpioPin_KBRow7,
+    NvOdmKbcGpioPin_KBRow8,
+    NvOdmKbcGpioPin_KBRow9,
+    NvOdmKbcGpioPin_KBRow10,
+    NvOdmKbcGpioPin_KBRow11,
+    NvOdmKbcGpioPin_KBRow12,
+    NvOdmKbcGpioPin_KBRow13,
+    NvOdmKbcGpioPin_KBRow14,
+    NvOdmKbcGpioPin_KBRow15,
+    NvOdmKbcGpioPin_KBCol0,
+    NvOdmKbcGpioPin_KBCol1,
+    NvOdmKbcGpioPin_KBCol2,
+    NvOdmKbcGpioPin_KBCol3,
+    NvOdmKbcGpioPin_KBCol4,
+    NvOdmKbcGpioPin_KBCol5,
+    NvOdmKbcGpioPin_KBCol6,
+    NvOdmKbcGpioPin_KBCol7,
+    NvOdmKbcGpioPin_Num,
+    NvOdmKbcGpioPin_Force32 = 0x7FFFFFFF
+}NvOdmKbcGpioPin;
+
+#endif // NVODM_QUERY_KBC_GPIO_DEF_H
+
diff --git a/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query_kbc_qwerty_def.h b/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query_kbc_qwerty_def.h
new file mode 100644
index 000000000000..c5c82bb5df35
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query_kbc_qwerty_def.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA APX ODM Kit::
+ *         The KBC qwerty property definitions</b>
+ *
+ * @b Description: Define the qwerty keyboard support definitions which is used
+ * by multiple functions.
+ */
+
+#ifndef NVODM_QUERY_KBC_QWERTY_DEF_H
+#define NVODM_QUERY_KBC_QWERTY_DEF_H
+
+#define KBC_QWERTY_NORMAL_KEY_CODE_BASE 0x1000
+#define KBC_QWERTY_FUNCTION_KEY_CODE_BASE 0x2000
+
+#define KBC_QWERTY_FUNCTION_KEY_ROW_BASE 0x100
+#define KBC_QWERTY_FUNCTION_KEY_ROW_NUMBER 0
+#define KBC_QWERTY_FUNCTION_KEY_COLUMN_NUMBER 7
+
+
+#endif // NVODM_QUERY_KBC_QWERTY_DEF_H
+
diff --git a/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query_nand.c b/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query_nand.c
new file mode 100644
index 000000000000..18a2c903cbb4
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query_nand.c
@@ -0,0 +1,255 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * @brief <b>NVIDIA Driver Development Kit:
+ *                  ODM Uart interface</b>
+ *
+ * @b Description: Implements the ODM for the Uart communication.
+ *
+ */
+
+#include "nvodm_query_nand.h"
+#include "nvcommon.h"
+
+// fill params for all required nand flashes here.
+// this list will end when vendor id and chipd id will be zero.
+// hence, all supported chips should be listed before that.
+NvOdmNandFlashParams g_Params[] =
+{
+    /*
+    {
+        VendorId, DeviceId, NandType, IsCopyBackCommandSupported, IsCacheWriteSupported, CapacityInMB, ZonesPerDevice,
+        BlocksPerZone, OperationSuccessStatus, InterleaveCapability, EccAlgorithm,
+        ErrorsCorrectable, SkippedSpareBytes,
+        TRP, TRH (TREH), TWP, TWH, TCS, TWHR, TWB, TREA, TADL,
+        TCLS, TCLH, TCH, TALS, TALH, TRC, TWC, TCR(TCLR), TAR, TRR, NandDeviceType, ReadIdFourthByte
+    }
+    Note :
+    TADL values for flashes K9F1G08Q0M, K9F1G08U0M, TH58NVG4D4CTG00,
+    TH58NVG3D4BTG00, TH58NVG2S3BFT00 is not available from their data sheets.
+    Hence TADL is computed as
+        tADL = (tALH + tALS + tWP).
+    */
+    // filling odm parameter structure for Samsung K9K8G08U0M
+    {
+        0xEC, 0xD3, NvOdmNandFlashType_Slc, NV_TRUE, NV_FALSE, 1024, 4,
+        2048, 0x40, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon,
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4,
+        15, 10, 15, 10, 20, 60, 100, 26, 70,
+        12, 5, 5, 12, 5, 25, 25, 10, 10, 20, NvOdmNandDeviceType_Type1, 0x95
+     },
+    // filling odm parameter structure for Samsung K9GAG08U0D
+    {
+        0xEC, 0xD5, NvOdmNandFlashType_Mlc, NV_TRUE, NV_FALSE, 2048, 2,
+        2048, 0x60, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon,
+        NvOdmNandNumberOfCorrectableSymbolErrors_Eight, NvOdmNandSkipSpareBytes_4,
+        15, 10, 15, 10, 20, 60, 100, 20, 100,
+        15, 5, 5, 15, 5, 30, 30, 10, 10, 20, NvOdmNandDeviceType_Type2, 0x29
+    },
+    // filling odm parameter structure for Samsung K9W8G08U1M
+    {
+        0xEC, 0xDC, NvOdmNandFlashType_Slc, NV_TRUE, NV_TRUE, 1024, 2,
+        4096, 0x60, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon,
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4,
+        15, 10, 15, 10, 15, 60, 100, 18, 100,
+        10, 5, 5, 10, 5, 30, 30, 10, 10, 20, NvOdmNandDeviceType_Type1, 0x15
+    },
+    // filling odm parameter structure for Samsung K9F1G08Q0M
+    {
+        0xEC, 0xA1, NvOdmNandFlashType_Slc, NV_TRUE, NV_TRUE, 128, 1,
+        1024, 0x60, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon,
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4,
+        60, 20, 60, 20, 0, 60, 100, 60, 70,
+        0, 10, 10, 0, 10, 80, 80, 10, 10, 20, NvOdmNandDeviceType_Type1, 0x15
+    },
+    // filling odm parameter structure for Samsung K9F1G08U0M
+    {
+        0xEC, 0xF1, NvOdmNandFlashType_Slc, NV_TRUE, NV_TRUE, 128, 1,
+        1024, 0x40, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon,
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4,
+        25, 15, 25, 15, 0, 60, 100, 30, 35,
+        0, 10, 10, 0, 10, 50, 45, 10, 10, 20, NvOdmNandDeviceType_Type1, 0x15
+     },
+    // filling odm parameter structure for Samsung K9L8G08U0M
+    {
+        0xEC, 0xD3, NvOdmNandFlashType_Mlc, NV_FALSE, NV_FALSE, 1024, 4,
+        1024, 0x40, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon,
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4,
+        15, 10, 15, 10, 20, 60, 100, 20, 35,
+        15, 5, 5, 15, 5, 30, 30, 10, 10, 20, NvOdmNandDeviceType_Type1, 0x25
+     },
+    // filling odm parameter structure for Samsung K9G4G08U0M
+    {
+        0xEC, 0xDC, NvOdmNandFlashType_Mlc, NV_FALSE, NV_FALSE, 512, 2,
+        1024, 0x40, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon,
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4,
+        15, 10, 15, 15, 15, 60, 100, 18, 50,
+        10, 5, 5, 10, 5, 30, 45, 10, 10, 20, NvOdmNandDeviceType_Type1, 0x25
+     },
+    // filling odm parameter structure for Samsung K5E2G1GACM
+    {
+        0xEC, 0xAA, NvOdmNandFlashType_Slc, NV_TRUE, NV_FALSE, 256, 2,
+        1024, 0x40, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon,
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4,
+        21, 15, 21, 15, 31, 60, 100, 30, 100,
+        21, 5, 5, 21, 5, 42, 42, 10, 10, 20, NvOdmNandDeviceType_Type1, 0x15
+     },
+/*
+    // filling odm parameter structure for Toshiba TH58NVG4D4CTG00
+    {
+        0x98, 0xD5, NvOdmNandFlashType_Mlc, NV_FALSE, NV_FALSE, 2048, 1,
+        8192, 0x40, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon,
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4,
+        41, 15, 15, 10, 0, 30, 20, 200, 41, 21,
+        0, 6, 6, 0, 6, NvOdmNandDeviceType_Type1, 0x25
+    },
+    // filling odm parameter structure for Toshiba TH58NVG3D4BTG00
+    {
+        0x98, 0xD3, NvOdmNandFlashType_Mlc, NV_FALSE, NV_TRUE, 1024, 1,
+        4096, 0x60, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon,
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4,
+        41, 15, 15, 10, 0, 30, 20, 200, 41, 35,
+        0, 10, 10, 0, 10, NvOdmNandDeviceType_Type1, 0x25
+     },
+    // filling odm parameter structure for Toshiba TH58NVG2S3BFT00
+    {
+        0x98, 0xDC, NvOdmNandFlashType_Slc, NV_FALSE, NV_FALSE, 512, 1,
+        1024, 0x60, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon,
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4,
+        41, 15, 15, 10, 0, 30, 20, 200, 41, 35,
+        0, 10, 10, 0, 10, NvOdmNandDeviceType_Type1, 0x25
+     },
+*/
+    // filling odm parameter structure for Samsung K9LBG08U0M
+    {
+        0xEC, 0xD7, NvOdmNandFlashType_Mlc, NV_TRUE, NV_FALSE, 4096, 4, 2048,
+        0x40, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon,
+        NvOdmNandNumberOfCorrectableSymbolErrors_Six, NvOdmNandSkipSpareBytes_4,
+        12, 10, 12, 10, 20, 60, 100, 20, 100,
+        12, 5, 5, 12, 5, 25, 25, 10, 10, 20, NvOdmNandDeviceType_Type1, 0xB6
+    },
+    //Hynix H8BES0UQ0MCP 
+     {
+        0xAD, 0xBC,  NvOdmNandFlashType_Slc, NV_TRUE, NV_FALSE, 512, 2, 2048, 
+        0x40, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon,  
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4, 
+        25, 10, 25, 15, 35, 60, 100, 30, 100,
+        25, 10, 10, 25, 10, 45, 45, 10, 10, 20, NvOdmNandDeviceType_Type1, 0x55
+     },
+     //Hynix H8BCS0SJ0MCP 
+    {
+        0xAD, 0xBA, NvOdmNandFlashType_Slc, NV_TRUE, NV_FALSE, 256, 1, 2048, 
+        0x60, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon,  
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4, 
+        25, 15, 25, 15, 35, 60, 100, 30, 100,
+        25, 10, 10, 25, 10, 45, 45, 10, 10, 25, NvOdmNandDeviceType_Type1, 0x55
+     },
+
+     //Hynix H8BCS0RJ0MCP 
+    {
+        0xAD, 0xAA, NvOdmNandFlashType_Slc, NV_TRUE, NV_FALSE, 256, 1, 2048, 
+        0x60, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon, 
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4, 
+        25, 10, 25, 15, 35, 60, 100, 30, 100,
+        25, 10, 10, 25, 10, 45, 45, 10, 10, 25, NvOdmNandDeviceType_Type1, 0x15
+     },
+     /*Numonyx MCP - NAND02GR3B2D*/ 
+    {
+        0x20, 0xAA, NvOdmNandFlashType_Slc, NV_TRUE, NV_FALSE, 256, 1, 
+        2048, 0x40, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon, 
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4,
+        25, 15, 25, 15, 35, 60, 100, 30, 100,
+        25, 10, 10, 25, 10, 45, 45, 10, 10, 25, NvOdmNandDeviceType_Type1, 0x15
+     },
+     // Hynix HY27UF084G2B (readid 4th byte 0x95)
+     {
+        0xAD, 0xDC, NvOdmNandFlashType_Slc, NV_TRUE, NV_FALSE, 512, 2,
+        2048, 0x60, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon, 
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4, 
+        12, 10, 12, 10, 20, 80, 100, 20, 70,
+        12, 5, 5, 12, 5, 25, 25, 10, 10, 20, NvOdmNandDeviceType_Type1, 0x95
+     },
+    /* "This is the end of device list please do not modify this. To add support for more flash parts,
+        add device category for those parts before this element"*/
+    {
+        0, 0, NvOdmNandFlashType_UnKnown, NV_FALSE, NV_FALSE, 0, 0,
+        0, 0, SINGLE_PLANE, NvOdmNandECCAlgorithm_ReedSolomon,
+        NvOdmNandNumberOfCorrectableSymbolErrors_Four, NvOdmNandSkipSpareBytes_4,
+        0, 0, 0, 0, 0, 0, 0, 0, 0,
+        0, 0, 0, 0, 0, 0, 0, 0, 0, 0, NvOdmNandDeviceType_Type1, 0
+    }
+};
+
+NvOdmNandFlashParams *NvOdmNandGetFlashInfo (NvU32 ReadID)
+{
+    NvU8 TempValue;
+    NvU8 VendorId = 0;
+    NvU8 DeviceId = 0;
+    NvU8 ReadIdFourthByte = 0;
+    NvOdmNandFlashType NandType;
+    NvU8 i = 0;
+    // To extract Vendor Id
+    VendorId = (NvU8) (ReadID & 0xFF);
+    // To extract Device Id
+    DeviceId = (NvU8) ((ReadID >> DEVICE_SHIFT) & 0xFF);
+    // To extract Fourth ID byte of Read ID - for checking if the flash is 42nm.
+    ReadIdFourthByte = (NvU8) ((ReadID >> FOURTH_ID_SHIFT) & 0xFF);
+    // To extract device Type Mask
+    TempValue = (NvU8) ((ReadID >> FLASH_TYPE_SHIFT) & 0xC);
+    if (TempValue)
+    {
+        NandType = NvOdmNandFlashType_Mlc;
+    }
+    else
+    {
+        NandType = NvOdmNandFlashType_Slc;
+    }
+    // following ORing is done to check if we reached the end of the list.
+    while ((g_Params[i].VendorId) | (g_Params[i].DeviceId))
+    {
+        if ((g_Params[i].VendorId == VendorId) &&
+            (g_Params[i].DeviceId == DeviceId) &&
+            (g_Params[i].ReadIdFourthByte == ReadIdFourthByte) &&
+            (g_Params[i].NandType == NandType))
+        {
+            return &g_Params[i];
+        }
+        else
+            i++;
+    }
+    // This condition will be reached if "g_Params" is not having Parameters of the flash used.
+    // Hence add the parameters required in the table.
+    return NULL;
+}
+
diff --git a/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query_pinmux.c b/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query_pinmux.c
new file mode 100644
index 000000000000..e8ec4b70b3dc
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/harmony/nvodm_query_pinmux.c
@@ -0,0 +1,305 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/*
+ * This file implements the pin-mux configuration tables for each I/O module.
+ */
+
+// THESE SETTINGS ARE PLATFORM-SPECIFIC (not SOC-specific).
+// PLATFORM = Harmony
+
+#include "nvodm_query_pinmux.h"
+#include "nvassert.h"
+#include "nvodm_query.h"
+#include "nvodm_services.h"
+
+#define NVODM_PINMUX_ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+
+static const NvU32 s_NvOdmPinMuxConfig_Uart[] = {
+    NvOdmUartPinMap_Config4,    // UART1, 2 lines
+    NvOdmUartPinMap_Config2,    // UART2, 2 lines
+    NvOdmUartPinMap_Config1,    // UART3, 4 lines
+    NvOdmUartPinMap_Config2,    // UART4, 4 lines
+    0                           // UART5
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Spi[] = {
+    NvOdmSpiPinMap_Config4,
+    0,
+    0,
+    0,
+    0
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Twc[] = {
+    0
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_I2c[] = {
+    NvOdmI2cPinMap_Config1,
+    NvOdmI2cPinMap_Config1,
+    NvOdmI2cPinMap_Config1
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_I2cPmu[] = {
+    NvOdmI2cPmuPinMap_Config1
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Ulpi[] = {
+    NvOdmUlpiPinMap_Config1
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Sdio[] = {
+    NvOdmSdioPinMap_Config1, 
+    NvOdmSdioPinMap_Config5,
+    0,
+    NvOdmSdioPinMap_Config2
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Spdif[] = {
+    NvOdmSpdifPinMap_Config2
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Hsi[] = {
+    0
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Hdcp[] = {
+    NvOdmHdcpPinMap_Config1
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Hdmi[] = {
+    NvOdmHdmiPinMap_Config1
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Pwm[] = {
+    NvOdmPwmPinMap_Config6
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Ata[] = {
+    0
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Nand[] = {
+    NvOdmNandPinMap_Config4, 
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Dap[] = {
+    NvOdmDapPinMap_Config1,
+    NvOdmDapPinMap_Config1, 
+    0, 
+    NvOdmDapPinMap_Config1,
+    0
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Kbd[] = {
+    NvOdmKbdPinMap_Config1
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_SyncNor[] = {
+    0
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Mio[] = {
+    0
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_ExternalClock[] = {
+    NvOdmExternalClockPinMap_Config2,  
+    NvOdmExternalClockPinMap_Config3,
+    NvOdmExternalClockPinMap_Config1
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_VideoInput[] = {
+    0
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Display[] = {
+    NvOdmDisplayPinMap_Config1,
+    0  // Only 1 display is connected to the LCD pins
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_BacklightPwm[] = {
+    0,
+    0
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Crt[] = {
+    NvOdmCrtPinMap_Config1,
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_Tvo[] = {
+    NvOdmTvoPinMap_Config1,
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_OneWire[] = {
+    0
+};
+
+static const NvU32 s_NvOdmPinMuxConfig_PciExpress[] = {
+    NvOdmPciExpressPinMap_Config1,
+};
+
+void
+NvOdmQueryPinMux(
+    NvOdmIoModule IoModule,
+    const NvU32 **pPinMuxConfigTable,
+    NvU32 *pCount)
+{
+    switch (IoModule)
+    {
+    case NvOdmIoModule_Display:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Display;
+        *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_Display);
+        break;
+
+    case NvOdmIoModule_Dap:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Dap;
+        *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_Dap);
+        break;
+
+    case NvOdmIoModule_Hdcp:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Hdcp;
+        *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_Hdcp);
+        break;
+
+    case NvOdmIoModule_Hdmi:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Hdmi;
+        *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_Hdmi);
+        break;
+
+    case NvOdmIoModule_I2c:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_I2c;
+        *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_I2c);
+        break;
+
+    case NvOdmIoModule_I2c_Pmu:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_I2cPmu;
+        *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_I2cPmu);
+        break;
+
+    case NvOdmIoModule_Nand:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Nand;
+        *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_Nand);
+        break;
+
+    case NvOdmIoModule_Sdio:
+       *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Sdio;
+       *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_Sdio);
+        break;
+
+    case NvOdmIoModule_Spi:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Spi;
+        *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_Spi);
+        break;
+
+    case NvOdmIoModule_Uart:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Uart;
+        *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_Uart);
+        break;
+
+    case NvOdmIoModule_ExternalClock:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_ExternalClock;
+        *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_ExternalClock);
+        break;
+    
+    case NvOdmIoModule_Crt:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Crt;
+        *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_Crt);
+        break;
+
+    case NvOdmIoModule_PciExpress:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_PciExpress;
+        *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_PciExpress); 
+        break;
+        
+    case NvOdmIoModule_Tvo:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Tvo;
+        *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_Tvo);
+        break;
+    case NvOdmIoModule_BacklightPwm:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_BacklightPwm;
+        *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_BacklightPwm);
+        break;
+
+    case NvOdmIoModule_Pwm:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Pwm;
+        *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_Pwm);
+        break;
+
+    case NvOdmIoModule_Ulpi:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Ulpi;
+        *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_Ulpi);
+        break;
+
+    case NvOdmIoModule_Spdif:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Spdif;
+        *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_Spdif);
+        break;
+
+    case NvOdmIoModule_Kbd:
+        *pPinMuxConfigTable = s_NvOdmPinMuxConfig_Kbd;
+        *pCount = NVODM_PINMUX_ARRAY_SIZE(s_NvOdmPinMuxConfig_Kbd);
+        break;
+
+    case NvOdmIoModule_Twc:
+    case NvOdmIoModule_Hsi:
+    case NvOdmIoModule_Ata:
+    case NvOdmIoModule_SyncNor:
+    case NvOdmIoModule_Mio:
+    case NvOdmIoModule_VideoInput:
+    case NvOdmIoModule_OneWire:
+        *pPinMuxConfigTable = NULL;
+        *pCount = 0;
+        break;
+
+    default:
+        *pCount = 0;
+        break;
+    }
+}
+
+void
+NvOdmQueryClockLimits(
+    NvOdmIoModule IoModule,
+    const NvU32 **pClockSpeedLimits,
+    NvU32 *pCount)
+{
+    switch (IoModule)
+    {
+        default:
+            *pClockSpeedLimits = NULL;
+            *pCount = 0;
+            break;
+    }
+}
+
diff --git a/arch/arm/mach-tegra/odm_kit/query/harmony/subboards/nvodm_query_discovery_e1162_addresses.h b/arch/arm/mach-tegra/odm_kit/query/harmony/subboards/nvodm_query_discovery_e1162_addresses.h
new file mode 100644
index 000000000000..000fd861577e
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/harmony/subboards/nvodm_query_discovery_e1162_addresses.h
@@ -0,0 +1,428 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA APX ODM Kit::
+ *         Implementation of the ODM Peripheral Discovery API</b>
+ *
+ * @b Description: Specifies the peripheral connectivity database NvOdmIoAddress entries
+ *                 for the peripherals on E1162 module.
+ */
+
+#include "pmu/tps6586x/nvodm_pmu_tps6586x_supply_info_table.h"
+#include "tmon/adt7461/nvodm_tmon_adt7461_channel.h"
+#include "nvodm_tmon.h"
+#include "../nvodm_query_kbc_gpio_def.h"
+
+
+// RTC voltage rail
+static const NvOdmIoAddress s_RtcAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO2 }  /* VDD_RTC -> LD02 */
+};
+
+// Core voltage rail
+static const NvOdmIoAddress s_CoreAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_DCD0 }  /* VDD_CORE -> SM0 */
+};
+
+// CPU voltage rail
+static const NvOdmIoAddress s_ffaCpuAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_DCD1 }  /* VDD_CPU -> SM1 */
+};
+
+// PLLA voltage rail
+static const NvOdmIoAddress s_PllAAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO1 } /* AVDDPLLX_1V2 -> LDO1 */
+};
+
+// PLLM voltage rail
+static const NvOdmIoAddress s_PllMAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO1 } /* AVDDPLLX_1V2 -> LDO1 */
+};
+
+// PLLP voltage rail
+static const NvOdmIoAddress s_PllPAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO1 } /* AVDDPLLX_1V2 -> LDO1 */
+};
+
+// PLLC voltage rail
+static const NvOdmIoAddress s_PllCAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO1 } /* AVDDPLLX_1V2 -> LDO1 */
+};
+
+// PLLE voltage rail
+static const NvOdmIoAddress s_PllEAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, Ext_TPS62290PmuSupply_BUCK } /* AVDD_PLLE -> VDD_1V05 */
+};
+
+// PLLU voltage rail
+static const NvOdmIoAddress s_PllUAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO1 } /* AVDD_PLLU -> LDO1 */
+};
+
+// PLLU1 voltage rail
+static const NvOdmIoAddress s_ffaPllU1Addresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO1 } /* AVDD_PLLU -> LDO1 */
+};
+
+// PLLS voltage rail
+static const NvOdmIoAddress s_PllSAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO1 } /* PLL_S -> LDO1 */
+};
+
+// PLLHD voltage rail
+static const NvOdmIoAddress s_PllHdmiAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO8 } /* AVDD_HDMI_PLL -> LDO8 */
+};
+
+// OSC voltage rail
+static const NvOdmIoAddress s_VddOscAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO4 } /* AVDD_OSC -> LDO4 */
+};
+
+// PLLX voltage rail
+static const NvOdmIoAddress s_PllXAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO1 } /* AVDDPLLX -> LDO1 */
+};
+
+// PLL_USB voltage rail
+static const NvOdmIoAddress s_PllUsbAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO3 } /* AVDD_USB_PLL -> derived from LDO3 (VDD_3V3) */
+};
+
+// SYS IO voltage rail
+static const NvOdmIoAddress s_VddSysAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO4 } /* VDDIO_SYS -> LDO4 */
+};
+
+// USB voltage rail
+static const NvOdmIoAddress s_VddUsbAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO3 } /* AVDD_USB -> derived from LDO3 (VDD_3V3) */
+};
+
+// HDMI voltage rail
+static const NvOdmIoAddress s_VddHdmiAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO7 } /* AVDD_HDMI -> LDO7 */
+};
+
+// MIPI voltage rail (DSI_CSI)
+static const NvOdmIoAddress s_VddMipiAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, Ext_TPS72012PmuSupply_LDO  } /* AVDD_DSI_CSI -> VDD_1V2 */
+};
+
+// LCD voltage rail
+static const NvOdmIoAddress s_VddLcdAddresses[] = 
+{
+    // This is in the AON domain
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO4 } /* VDDIO_LCD -> (LDO4PG) */
+};
+
+// Audio voltage rail
+static const NvOdmIoAddress s_VddAudAddresses[] = 
+{
+    // This is in the AON domain
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO4 } /* VDDIO_AUDIO -> (LDO4PG) */
+};
+
+// DDR voltage rail
+static const NvOdmIoAddress s_VddDdrAddresses[] = 
+{
+    // This is in the AON domain
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO4 }  /* VDDIO_DDR -> (LDO4PG) */
+};
+
+// DDR_RX voltage rail
+static const NvOdmIoAddress s_VddDdrRxAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO9 }  /* VDDIO_RX_DDR(2.7-3.3) -> LDO9 */
+};
+
+// NAND voltage rail
+static const NvOdmIoAddress s_VddNandAddresses[] = 
+{
+    // This is in the AON domain
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO3 }  /* VDDIO_NAND_3V3 -> derived from LDO3 (VDD_3V3) */
+};
+
+// UART voltage rail
+static const NvOdmIoAddress s_VddUartAddresses[] = 
+{
+    // This is in the AON domain
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO4 } /* VDDIO_UART -> (LDO4PG) */
+};
+
+// SDIO voltage rail
+static const NvOdmIoAddress s_VddSdioAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO3 } /* VDDIO_SDIO -> derived from LDO3 (VDD_3V3) */
+};
+
+// VDAC voltage rail
+static const NvOdmIoAddress s_VddVdacAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO6 } /* AVDD_VDAC -> LDO6 */
+};
+
+// VI voltage rail
+static const NvOdmIoAddress s_VddViAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO3 } /* VDDIO_VI -> derived from LDO3 (VDD_3V3) */
+};
+
+// BB voltage rail
+static const NvOdmIoAddress s_VddBbAddresses[] = 
+{
+    // This is in the AON domain
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO4 } /* VDDIO_BB -> (LDO4PG) */
+};
+
+// Super power voltage rail for the SOC
+static const NvOdmIoAddress s_VddSocAddresses[]=
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_SoC } /* VDD SOC */
+};
+
+// PEX_CLK voltage rail
+static const NvOdmIoAddress s_VddPexClkAddresses[] = 
+{
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO0 }, /* VDDIO_PEX_CLK -> LDO0 */
+    { NvOdmIoModule_Vdd, 0x00, Ext_TPS62290PmuSupply_BUCK }, /* AVDD_PLLE -> VDD_1V05 */
+    { NvOdmIoModule_Vdd, 0x00, Ext_TPS74201PmuSupply_LDO }, /* PMU_GPIO-1 -> VDD_1V5 */
+};
+
+// PMU0
+static const NvOdmIoAddress s_Pmu0Addresses[] = 
+{
+    { NvOdmIoModule_I2c_Pmu, 0x00, 0x68 },
+};
+
+// SPI1 for Spi Ethernet Kitl only
+static const NvOdmIoAddress s_SpiEthernetAddresses[] =
+{
+    { NvOdmIoModule_Spi, 0, 0 },
+    { NvOdmIoModule_Gpio, (NvU32)'c'-'a', 1 },  // DBQ_IRQ, Port C, Pin 1
+};
+
+// P1160 ULPI USB
+static const NvOdmIoAddress s_UlpiUsbAddresses[] = 
+{
+    { NvOdmIoModule_ExternalClock, 1, 0 }, /* ULPI PHY Clock -> DAP_MCLK2 */
+};
+
+//  LVDS LCD Display
+static const NvOdmIoAddress s_LvdsDisplayAddresses[] = 
+{
+    { NvOdmIoModule_Display, 0, 0 },
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO4},     /* VDDIO_LCD (AON:VDD_1V8) */
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO3 },    /* VDD_LVDS (VDD_3V3) */
+};
+
+//  HDMI addresses based on Concorde 2 design
+static const NvOdmIoAddress s_HdmiAddresses[] =
+{
+    { NvOdmIoModule_Hdmi, 0, 0 },
+
+    // Display Data Channel (DDC) for Extended Display Identification
+    // Data (EDID)
+    { NvOdmIoModule_I2c, 0x01, 0xA0 },
+
+    // HDCP ROM
+    { NvOdmIoModule_I2c, 0x01, 0x74 },
+
+    /* AVDD_HDMI */
+    { NvOdmIoModule_Vdd, 0x00, Ext_TPS2051BPmuSupply_VDDIO_VID },   // VDDIO_HDMI
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO8 },            // AVDD_HDMI_PLL
+
+    /* lcd i/o rail (for hot plug pin) */
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO4 },    // VDDIO_LCD (VDD_1V8)
+};
+
+// CRT address based on Concorde 2 design
+static const NvOdmIoAddress s_CrtAddresses[] =
+{
+    { NvOdmIoModule_Crt, 0, 0 },
+
+    // Display Data Channel (DDC) for Extended Display Identification
+    // Data (EDID)
+    // FIXME: Disable this for now since it causes some TV not display.
+    { NvOdmIoModule_I2c, 0x01, 0xA0 },
+
+    /* tvdac rail */
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO6 },    // VDDIO_VDAC
+
+    /* lcd rail (required for crt out) */
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO4 },    // VDDIO_LCD (VDD_1V8)
+    { NvOdmIoModule_Vdd, 0x00, Ext_TPS2051BPmuSupply_VDDIO_VID },   // VDDIO_VGA
+};
+
+static const NvOdmIoAddress s_ffaVideoDacAddresses[] =
+{
+    { NvOdmIoModule_Tvo, 0x00, 0x00 },
+    /* tvdac rail */
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO6 },    // AVDD_VDAC
+};
+
+// Sdio
+static const NvOdmIoAddress s_SdioAddresses[] =
+{
+    { NvOdmIoModule_Sdio, 0x1,  0x0 },                      /* SD Memory on SD Bus */
+    { NvOdmIoModule_Sdio, 0x3,  0x0 },                      /* SD Memory on SD Bus */
+    { NvOdmIoModule_Vdd,  0x00, Ext_SWITCHPmuSupply_VDDIO_SD },   /* EN_VDDIO_SD */
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO3 } /* VDDIO_SDIO -> derived from LDO3 (VDD_3V3) */
+};
+
+static const NvOdmIoAddress s_I2cSmbusAddresses[] = 
+{
+    { NvOdmIoModule_I2c, 2, 0x8A },
+    { NvOdmIoModule_Gpio, 27, 1} //Port BB:01 is used on harmony. 
+};
+
+static const NvOdmIoAddress s_UsbMuxAddress[] = 
+{
+    {NvOdmIoModule_Usb, 1, 0}
+};
+
+static const NvOdmIoAddress s_QwertyKeyPad16x8Addresses[] =
+{
+    // instance = 1 indicates Column info.
+    // instance = 0 indicates Row info.
+    // address holds KBC pin number used for row/column.
+
+    // All Row info has to be defined contiguously from 0 to max.
+    { NvOdmIoModule_Kbd, 0x00, NvOdmKbcGpioPin_KBRow0}, // Row 0
+    { NvOdmIoModule_Kbd, 0x00, NvOdmKbcGpioPin_KBRow1}, // Row 1
+    { NvOdmIoModule_Kbd, 0x00, NvOdmKbcGpioPin_KBRow2}, // Row 2
+    { NvOdmIoModule_Kbd, 0x00, NvOdmKbcGpioPin_KBRow3}, // Row 3
+    { NvOdmIoModule_Kbd, 0x00, NvOdmKbcGpioPin_KBRow4}, // Row 4
+    { NvOdmIoModule_Kbd, 0x00, NvOdmKbcGpioPin_KBRow5}, // Row 5
+    { NvOdmIoModule_Kbd, 0x00, NvOdmKbcGpioPin_KBRow6}, // Row 6
+    { NvOdmIoModule_Kbd, 0x00, NvOdmKbcGpioPin_KBRow7}, // Row 7
+    { NvOdmIoModule_Kbd, 0x00, NvOdmKbcGpioPin_KBRow8}, // Row 8
+    { NvOdmIoModule_Kbd, 0x00, NvOdmKbcGpioPin_KBRow9}, // Row 9
+    { NvOdmIoModule_Kbd, 0x00, NvOdmKbcGpioPin_KBRow10}, // Row 10
+    { NvOdmIoModule_Kbd, 0x00, NvOdmKbcGpioPin_KBRow11}, // Row 11
+    { NvOdmIoModule_Kbd, 0x00, NvOdmKbcGpioPin_KBRow12}, // Row 12
+    { NvOdmIoModule_Kbd, 0x00, NvOdmKbcGpioPin_KBRow13}, // Row 13
+    { NvOdmIoModule_Kbd, 0x00, NvOdmKbcGpioPin_KBRow14}, // Row 14
+    { NvOdmIoModule_Kbd, 0x00, NvOdmKbcGpioPin_KBRow15}, // Row 15
+    
+    // All Column info has to be defined contiguously from 0 to max.
+    { NvOdmIoModule_Kbd, 0x01, NvOdmKbcGpioPin_KBCol0}, // Column 0
+    { NvOdmIoModule_Kbd, 0x01, NvOdmKbcGpioPin_KBCol1}, // Column 1
+    { NvOdmIoModule_Kbd, 0x01, NvOdmKbcGpioPin_KBCol2}, // Column 2
+    { NvOdmIoModule_Kbd, 0x01, NvOdmKbcGpioPin_KBCol3}, // Column 3
+    { NvOdmIoModule_Kbd, 0x01, NvOdmKbcGpioPin_KBCol4}, // Column 4
+    { NvOdmIoModule_Kbd, 0x01, NvOdmKbcGpioPin_KBCol5}, // Column 5
+    { NvOdmIoModule_Kbd, 0x01, NvOdmKbcGpioPin_KBCol6}, // Column 6
+    { NvOdmIoModule_Kbd, 0x01, NvOdmKbcGpioPin_KBCol7}, // Column 7
+};
+
+
+static const NvOdmIoAddress s_Tmon0Addresses[] = 
+{
+    { NvOdmIoModule_I2c_Pmu, 0x00, 0x98 },                  /* I2C bus */
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO3 },    /* TMON pwer rail -> LDO3 (VDD_3V3) */
+    { NvOdmIoModule_Gpio, (NvU32)'n'-'a', 6 },              /* GPIO Port N and Pin 6 */
+
+    /* Temperature zone mapping */
+    { NvOdmIoModule_Tsense, NvOdmTmonZoneID_Core, ADT7461ChannelID_Remote },   /* TSENSOR */
+    { NvOdmIoModule_Tsense, NvOdmTmonZoneID_Ambient, ADT7461ChannelID_Local }, /* TSENSOR */
+};
+
+// Bluetooth
+static const NvOdmIoAddress s_p1162BluetoothAddresses[] =
+{
+    { NvOdmIoModule_Uart, 0x2,  0x0 },                  // FIXME: Is this used?
+    { NvOdmIoModule_Gpio, (NvU32)'u'-'a', 0 },          /* BT_RST#: GPIO Port U and Pin 0 */
+    { NvOdmIoModule_Vdd, 0x00, TPS6586xPmuSupply_LDO4 } /* VDDHOSTIF_BT -> LDO4 (AON:VDD_1V8) */
+};
+
+// Wlan
+static const NvOdmIoAddress s_WlanAddresses[] =
+{
+    { NvOdmIoModule_Sdio, 0x0, 0x0 },                      /* WLAN is on SD Bus */
+    { NvOdmIoModule_Gpio, 0xa, 0x5 },                      /* GPIO Port K and Pin 5 - WIFI_PWR*/
+    { NvOdmIoModule_Gpio, 0xa, 0x6 },                      /* GPIO Port K and Pin 6 - WIFI_RST */
+    { NvOdmIoModule_Vdd,  0x00, TPS6586xPmuSupply_LDO4 },  /* VDDIO_WLAN (AON:VDD_1V8) */
+    { NvOdmIoModule_Vdd,  0x00, Ext_TPS72012PmuSupply_LDO } /* VCORE_WIFI (VDD_1V2) */
+};
+
+// Audio Codec
+static const NvOdmIoAddress s_AudioCodecAddresses[] = 
+{
+    { NvOdmIoModule_ExternalClock, 0, 0 },       /* Codec MCLK -> APxx DAP_MCLK1 */
+    { NvOdmIoModule_I2c_Pmu, 0x00, 0x34 },       /* Codec I2C ->  APxx PMU I2C, segment 0 */
+                                                 /* Codec I2C address is 0x34 */
+};
+
+// Audio Codec on GEN1_I2C (I2C_1)
+static const NvOdmIoAddress s_AudioCodecAddressesI2C_1[] = 
+{
+    { NvOdmIoModule_ExternalClock, 0, 0 },       /* Codec MCLK -> APxx DAP_MCLK1 */
+    { NvOdmIoModule_I2c, 0x00, 0x34 },           /* Codec I2C ->  APxx PMU I2C, segment 0 */
+                                                 /* Codec I2C address is 0x34 */
+};
+
+// TouchPanel
+static const NvOdmIoAddress s_TouchPanelAddresses[] = 
+{
+    { NvOdmIoModule_I2c_Pmu, 0x00, 0x06 }, /* I2C address (7-bit) 0x03<<1=0x06(8-bit)  */
+    { NvOdmIoModule_Gpio, (NvU32)'d'-'a', 0x02 }, /* GPIO Port D and Pin 2 */
+};
+
+static const NvOdmIoAddress s_AcceleroAddresses[] =
+{
+    { NvOdmIoModule_I2c_Pmu, 0x00, 0x70 }, /* I2C address (7-bit) 0x38<<1 = 0x70(8-bit) */
+    { NvOdmIoModule_Gpio, (NvU32)'c'-'a', 0x03 }, /* Gpio port C and Pin 3 */
+};
+
+
diff --git a/arch/arm/mach-tegra/odm_kit/query/harmony/subboards/nvodm_query_discovery_e1162_peripherals.h b/arch/arm/mach-tegra/odm_kit/query/harmony/subboards/nvodm_query_discovery_e1162_peripherals.h
new file mode 100644
index 000000000000..df91cc1e6d22
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/harmony/subboards/nvodm_query_discovery_e1162_peripherals.h
@@ -0,0 +1,453 @@
+/*
+ * Copyright (c) 2007-2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA APX ODM Kit::
+ *         Implementation of the ODM Peripheral Discovery API</b>
+ *
+ * @b Description: Specifies the peripheral connectivity database Peripheral entries
+ *                 for the peripherals on P1162 module.
+ */
+// AP20 doesn't have PLL_D rail.
+// PLLD (NV reserved) / Use PLL_U
+{
+    NV_VDD_PLLD_ODM_ID,
+    s_PllUAddresses,
+    NV_ARRAY_SIZE(s_PllUAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// RTC (NV reserved)
+{
+    NV_VDD_RTC_ODM_ID,
+    s_RtcAddresses,
+    NV_ARRAY_SIZE(s_RtcAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// CORE (NV reserved)
+{
+    NV_VDD_CORE_ODM_ID,
+    s_CoreAddresses,
+    NV_ARRAY_SIZE(s_CoreAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// CPU (NV reserved)
+{
+    NV_VDD_CPU_ODM_ID,
+    s_ffaCpuAddresses,
+    NV_ARRAY_SIZE(s_ffaCpuAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// PLLA (NV reserved)
+{
+    NV_VDD_PLLA_ODM_ID,
+    s_PllAAddresses,
+    NV_ARRAY_SIZE(s_PllAAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// PLLM (NV reserved)
+{
+    NV_VDD_PLLM_ODM_ID,
+    s_PllMAddresses,
+    NV_ARRAY_SIZE(s_PllMAddresses),
+    NvOdmPeripheralClass_Other
+},
+    
+// PLLP (NV reserved)
+{
+    NV_VDD_PLLP_ODM_ID,
+    s_PllPAddresses,
+    NV_ARRAY_SIZE(s_PllPAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// PLLC (NV reserved)
+{
+    NV_VDD_PLLC_ODM_ID,
+    s_PllCAddresses,
+    NV_ARRAY_SIZE(s_PllCAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// PLLE (NV reserved)
+{
+    NV_VDD_PLLE_ODM_ID,
+    s_PllEAddresses,
+    NV_ARRAY_SIZE(s_PllEAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// PLLU (NV reserved)
+{
+    NV_VDD_PLLU_ODM_ID,
+    s_PllUAddresses,
+    NV_ARRAY_SIZE(s_PllUAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// PLLU1 (NV reserved)
+{
+    NV_VDD_PLLU1_ODM_ID,
+    s_ffaPllU1Addresses,
+    NV_ARRAY_SIZE(s_ffaPllU1Addresses),
+    NvOdmPeripheralClass_Other
+},
+
+// PLLS (NV reserved)
+{
+    NV_VDD_PLLS_ODM_ID,
+    s_PllSAddresses,
+    NV_ARRAY_SIZE(s_PllSAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// HDMI PLL (NV reserved)
+{
+    NV_VDD_PLLHDMI_ODM_ID,
+    s_PllHdmiAddresses,
+    NV_ARRAY_SIZE(s_PllHdmiAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// OSC VDD (NV reserved)
+{
+    NV_VDD_OSC_ODM_ID,
+    s_VddOscAddresses,
+    NV_ARRAY_SIZE(s_VddOscAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// PLLX (NV reserved)
+{
+    NV_VDD_PLLX_ODM_ID,
+    s_PllXAddresses,
+    NV_ARRAY_SIZE(s_PllXAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// PLL_USB (NV reserved)
+{
+    NV_VDD_PLL_USB_ODM_ID,
+    s_PllUsbAddresses,
+    NV_ARRAY_SIZE(s_PllUsbAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// System IO VDD (NV reserved)
+{
+    NV_VDD_SYS_ODM_ID,
+    s_VddSysAddresses,
+    NV_ARRAY_SIZE(s_VddSysAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// USB VDD (NV reserved)
+{
+    NV_VDD_USB_ODM_ID,
+    s_VddUsbAddresses,
+    NV_ARRAY_SIZE(s_VddUsbAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// HDMI VDD (NV reserved)
+{
+    NV_VDD_HDMI_ODM_ID,
+    s_VddHdmiAddresses,
+    NV_ARRAY_SIZE(s_VddHdmiAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// MIPI VDD (NV reserved) / AVDD_DSI_CSI
+{
+    NV_VDD_MIPI_ODM_ID,
+    s_VddMipiAddresses,
+    NV_ARRAY_SIZE(s_VddMipiAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// LCD VDD (NV reserved)
+{
+    NV_VDD_LCD_ODM_ID,
+    s_VddLcdAddresses,
+    NV_ARRAY_SIZE(s_VddLcdAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// AUDIO VDD (NV reserved)
+{
+    NV_VDD_AUD_ODM_ID,
+    s_VddAudAddresses,
+    NV_ARRAY_SIZE(s_VddAudAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// DDR VDD (NV reserved)
+{
+    NV_VDD_DDR_ODM_ID,
+    s_VddDdrAddresses,
+    NV_ARRAY_SIZE(s_VddDdrAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// DDR_RX (NV reserved)
+{
+    NV_VDD_DDR_RX_ODM_ID,
+    s_VddDdrRxAddresses,
+    NV_ARRAY_SIZE(s_VddDdrRxAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// NAND VDD (NV reserved)
+{
+    NV_VDD_NAND_ODM_ID,
+    s_VddNandAddresses,
+    NV_ARRAY_SIZE(s_VddNandAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// UART VDD (NV reserved)
+{
+    NV_VDD_UART_ODM_ID,
+    s_VddUartAddresses,
+    NV_ARRAY_SIZE(s_VddUartAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// SDIO VDD (NV reserved)
+{
+    NV_VDD_SDIO_ODM_ID,
+    s_VddSdioAddresses,
+    NV_ARRAY_SIZE(s_VddSdioAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// VDAC VDD (NV reserved)
+{
+    NV_VDD_VDAC_ODM_ID,
+    s_VddVdacAddresses,
+    NV_ARRAY_SIZE(s_VddVdacAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// VI VDD (NV reserved)
+{
+    NV_VDD_VI_ODM_ID,
+    s_VddViAddresses,
+    NV_ARRAY_SIZE(s_VddViAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// BB VDD (NV reserved)
+{
+    NV_VDD_BB_ODM_ID,
+    s_VddBbAddresses,
+    NV_ARRAY_SIZE(s_VddBbAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// PEX_CLK (NV reserved)
+{
+    NV_VDD_PEX_CLK_ODM_ID,
+    s_VddPexClkAddresses,
+    NV_ARRAY_SIZE(s_VddPexClkAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+#if 0
+//  VBUS
+{
+    NV_VDD_VBUS_ODM_ID,
+    s_VddVBusAddresses,
+    NV_ARRAY_SIZE(s_VddVBusAddresses),
+    NvOdmPeripheralClass_Other
+},
+#endif
+
+//SOC
+{
+    NV_VDD_SoC_ODM_ID,
+    s_VddSocAddresses,
+    NV_ARRAY_SIZE(s_VddSocAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+//  PMU0
+{
+    NV_ODM_GUID('t','p','s','6','5','8','6','x'),
+    s_Pmu0Addresses,
+    NV_ARRAY_SIZE(s_Pmu0Addresses),
+    NvOdmPeripheralClass_Other
+},
+
+//  ENC28J60 SPI Ethernet module
+{
+    NV_ODM_GUID('e','n','c','2','8','j','6','0'),
+    s_SpiEthernetAddresses,
+    NV_ARRAY_SIZE(s_SpiEthernetAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+//  SMSC3317 ULPI USB PHY
+{
+    NV_ODM_GUID('s','m','s','c','3','3','1','7'),
+    s_UlpiUsbAddresses,
+    NV_ARRAY_SIZE(s_UlpiUsbAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+//  LVDS LCD Display
+{
+    NV_ODM_GUID('L','V','D','S','W','S','V','G'),   // LVDS WSVGA panel
+    s_LvdsDisplayAddresses,
+    NV_ARRAY_SIZE(s_LvdsDisplayAddresses),
+    NvOdmPeripheralClass_Display
+},
+
+// HDMI (based on Concorde 2 design)
+{
+    NV_ODM_GUID('f','f','a','2','h','d','m','i'),
+    s_HdmiAddresses,
+    NV_ARRAY_SIZE(s_HdmiAddresses),
+    NvOdmPeripheralClass_Display    
+},
+
+// CRT (based on Concorde 2 design)
+{
+    NV_ODM_GUID('f','f','a','_','_','c','r','t'),
+    s_CrtAddresses,
+    NV_ARRAY_SIZE(s_CrtAddresses),
+    NvOdmPeripheralClass_Display
+},
+
+// TV Out Video Dac
+{
+    NV_ODM_GUID('f','f','a','t','v','o','u','t'),
+    s_ffaVideoDacAddresses,
+    NV_ARRAY_SIZE(s_ffaVideoDacAddresses),
+    NvOdmPeripheralClass_Display
+},
+
+// Sdio
+{
+    NV_ODM_GUID('s','d','i','o','_','m','e','m'),
+    s_SdioAddresses,
+    NV_ARRAY_SIZE(s_SdioAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// I2c SmBus transport.
+{
+    NV_ODM_GUID('I','2','c','S','m','B','u','s'),
+    s_I2cSmbusAddresses,
+    NV_ARRAY_SIZE(s_I2cSmbusAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// USB Mux J7A1 and J6A1
+{
+   NV_ODM_GUID('u','s','b','m','x','J','7','6'),
+    s_UsbMuxAddress,
+    NV_ARRAY_SIZE(s_UsbMuxAddress),
+    NvOdmPeripheralClass_Other
+
+},
+
+// Qwerty key baord for 16x8
+{
+    NV_ODM_GUID('q','w','e','r','t','y',' ',' '),
+    s_QwertyKeyPad16x8Addresses,
+    NV_ARRAY_SIZE(s_QwertyKeyPad16x8Addresses),
+    NvOdmPeripheralClass_HCI
+},
+
+// Temperature Monitor (TMON)
+{
+    NV_ODM_GUID('a','d','t','7','4','6','1',' '),
+    s_Tmon0Addresses,
+    NV_ARRAY_SIZE(s_Tmon0Addresses),
+    NvOdmPeripheralClass_Other
+},
+
+// Bluetooth
+{
+    NV_ODM_GUID('b','l','u','t','o','o','t','h'),
+    s_p1162BluetoothAddresses,
+    NV_ARRAY_SIZE(s_p1162BluetoothAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// Sdio wlan  on COMMs Module
+{
+    NV_ODM_GUID('s','d','i','o','w','l','a','n'),
+    s_WlanAddresses,
+    NV_ARRAY_SIZE(s_WlanAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// Audio codec (I2C_PMU edition)
+{
+    NV_ODM_GUID('w','o','l','f','8','9','0','3'),
+    s_AudioCodecAddresses,
+    NV_ARRAY_SIZE(s_AudioCodecAddresses),
+    NvOdmPeripheralClass_Other
+},
+
+// Audio codec (I2C_1 edition)
+{
+    NV_ODM_GUID('w','o','8','9','0','3','_','1'),
+    s_AudioCodecAddressesI2C_1,
+    NV_ARRAY_SIZE(s_AudioCodecAddressesI2C_1),
+    NvOdmPeripheralClass_Other
+},
+
+// Touch panel
+{
+    NV_ODM_GUID('p','a','n','j','i','t','_','0'),
+    s_TouchPanelAddresses,
+    NV_ARRAY_SIZE(s_TouchPanelAddresses),
+    NvOdmPeripheralClass_HCI
+},
+
+// Accelerometer Module
+{
+    NV_ODM_GUID('b','m','a','1','5','0','a','c'),
+    s_AcceleroAddresses,
+    NV_ARRAY_SIZE(s_AcceleroAddresses),
+    NvOdmPeripheralClass_Other,
+},
+
+// NOTE: This list *must* end with a trailing comma.
diff --git a/arch/arm/mach-tegra/odm_kit/query/harmony/tegra_devkit_custopt.h b/arch/arm/mach-tegra/odm_kit/query/harmony/tegra_devkit_custopt.h
new file mode 100644
index 000000000000..1ec701091145
--- /dev/null
+++ b/arch/arm/mach-tegra/odm_kit/query/harmony/tegra_devkit_custopt.h
@@ -0,0 +1,153 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * <b>NVIDIA Tegra ODM Kit:
+ *         Definition of bitfields inside the BCT customer option</b>
+ *
+ * @b Description: Defines the board-specific bitfields of the 
+ *                 BCT customer option parameter, for NVIDIA
+ *                 Tegra development platforms.
+ *  
+ *                 This file pertains to Whistler and Voyager.
+ */
+
+#ifndef NVIDIA_TEGRA_DEVKIT_CUSTOPT_H
+#define NVIDIA_TEGRA_DEVKIT_CUSTOPT_H
+
+#if defined(__cplusplus)
+extern "C"
+{
+#endif
+
+//---------- BOARD PERSONALITIES (BEGIN) ----------//
+// On the Whistler boards, be sure to match the following
+// switches with the personality setting you choose.
+// 
+//      SW2 = bits 3:0 (low nibble)
+//      SW3 = bits 7:4 (high nibble)
+
+#define TEGRA_DEVKIT_DEFAULT_PERSONALITY \
+    TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_75
+
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_RANGE     7:0
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_DEFAULT  0x0UL
+
+// VOYAGER, eMMC, NO TRACE (10x8 keypad)
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_01       0x01UL  // ULPI = baseband
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_05       0x05UL  // ULPI = UART1
+
+// VOYAGER, eMMC, with TRACE (7x1 keypad)
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_11       0x11UL  // ULPI = baseband
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_15       0x15UL  // ULPI = UART1
+
+// VOYAGER, NAND, NO TRACE (10x8 keypad)
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_75       0x75UL  // Voyager, NAND
+
+// WHISTLER, stand-alone
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_C1       0xC1UL  // KB = 13x1, TRACE, GMI = A/D NOR
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_C3       0xC3UL  // KB = 16x8, NO TRACE, GMI = NAND
+
+// VOYAGER, USB2-ULPI (No UART1)
+// Personality 71 is similar to the 75, except ULPI is enabled instead of UART1.
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_PERSONALITY_71       0x71UL  
+
+
+//---------- BOARD PERSONALITIES (END) ----------//
+
+/// Download transport
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_TRANSPORT_RANGE      10:8
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_TRANSPORT_DEFAULT    0x0UL
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_TRANSPORT_NONE       0x1UL
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_TRANSPORT_UART       0x2UL
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_TRANSPORT_USB        0x3UL
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_TRANSPORT_ETHERNET   0x4UL
+
+/// Transport option (bus selector), for UART and Ethernet transport
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_UART_OPTION_RANGE   12:11
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_UART_OPTION_DEFAULT 0x0UL
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_UART_OPTION_A       0x1UL
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_UART_OPTION_B       0x2UL
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_UART_OPTION_C       0x3UL
+
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_ETHERNET_OPTION_RANGE   12:11
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_ETHERNET_OPTION_DEFAULT 0x0UL
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_ETHERNET_OPTION_SPI     0x1UL
+
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_OPTION_RANGE    17:15
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_OPTION_DEFAULT  0
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_OPTION_UARTA    0
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_OPTION_UARTB    1
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_OPTION_UARTC    2
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_OPTION_UARTD    3
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_OPTION_UARTE    4
+
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_RANGE           19:18
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_DEFAULT         0
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_NONE            1
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_DCC             2
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_CONSOLE_UART            3
+
+// display options
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_DISPLAY_OPTION_RANGE      22:20
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_DISPLAY_OPTION_DEFAULT    0x0UL
+// embedded panel (lvds, dsi, etc)
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_DISPLAY_OPTION_EMBEDDED   0x0UL
+// no panels (external or embedded)
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_DISPLAY_OPTION_NULL       0x1UL
+// use hdmi as the primary
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_DISPLAY_OPTION_HDMI       0x2UL
+// use crt as the primary 
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_DISPLAY_OPTION_CRT        0x3UL
+
+// Enable DHCP
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_DHCP_RANGE           23:23
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_DHCP_DEFAULT         0x0UL
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_DHCP_ENABLE          0x1UL
+
+/// Total RAM
+#define TEGRA_DEVKIT_BCT_SYSTEM_0_MEMORY_RANGE    30:28
+#define TEGRA_DEVKIT_BCT_SYSTEM_0_MEMORY_DEFAULT  0x0UL // 512 MB
+#define TEGRA_DEVKIT_BCT_SYSTEM_0_MEMORY_256      0x1UL // 256 MB
+#define TEGRA_DEVKIT_BCT_SYSTEM_0_MEMORY_512      0x2UL // 512 MB
+#define TEGRA_DEVKIT_BCT_SYSTEM_0_MEMORY_1024     0x3UL // 1024 MB (1 GB)
+
+/// Soc low power state
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_LPSTATE_RANGE            31:31
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_LPSTATE_LP0              0x0UL
+#define TEGRA_DEVKIT_BCT_CUSTOPT_0_LPSTATE_LP1              0x1UL
+#if defined(__cplusplus)
+}
+#endif
+
+#endif