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authorKerwin Wan <kerwinw@nvidia.com>2013-10-25 17:25:41 +0800
committerMitch Luban <mluban@nvidia.com>2013-11-26 13:26:09 -0800
commitbca2d14c7441c4cb761a4db5d5df45b2ec7c8571 (patch)
treecd6b54a65172dbcd3b2d3492241f999d5cc4b6a2 /arch/arm/mach-tegra/panel-p-wuxga-10-1.c
parent07652ce042033626c4fc47249307fd6f56b5ba25 (diff)
arm: tegra: move sd_settings to the panel board file
The configurable data of PRISM should be tuned per panel. So PRISM settings are needed to move from board-<platform>-panel.c to the specific panel board file. Bug 1391869 Change-Id: I70d28d7813cb21fc46a421a40e3cf53cb98d4a03 Signed-off-by: Kerwin Wan <kerwinw@nvidia.com> Reviewed-on: http://git-master/r/303813 Reviewed-by: Mitch Luban <mluban@nvidia.com> Tested-by: Mitch Luban <mluban@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/panel-p-wuxga-10-1.c')
-rw-r--r--arch/arm/mach-tegra/panel-p-wuxga-10-1.c50
1 files changed, 50 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/panel-p-wuxga-10-1.c b/arch/arm/mach-tegra/panel-p-wuxga-10-1.c
index cb0e9a0e4550..40c749c83d07 100644
--- a/arch/arm/mach-tegra/panel-p-wuxga-10-1.c
+++ b/arch/arm/mach-tegra/panel-p-wuxga-10-1.c
@@ -56,6 +56,55 @@ static struct regulator *vdd_ds_1v8;
#define en_vdd_bl TEGRA_GPIO_PG0
#define lvds_en TEGRA_GPIO_PG3
+static struct tegra_dc_sd_settings dsi_p_wuxga_10_1_sd_settings = {
+ .enable = 1, /* enabled by default. */
+ .use_auto_pwm = false,
+ .hw_update_delay = 0,
+ .bin_width = -1,
+ .aggressiveness = 5,
+ .use_vid_luma = false,
+ .phase_in_adjustments = 0,
+ .k_limit_enable = true,
+ .k_limit = 200,
+ .sd_window_enable = false,
+ .soft_clipping_enable = true,
+ /* Low soft clipping threshold to compensate for aggressive k_limit */
+ .soft_clipping_threshold = 128,
+ .smooth_k_enable = true,
+ .smooth_k_incr = 4,
+ /* Default video coefficients */
+ .coeff = {5, 9, 2},
+ .fc = {0, 0},
+ /* Immediate backlight changes */
+ .blp = {1024, 255},
+ /* Gammas: R: 2.2 G: 2.2 B: 2.2 */
+ /* Default BL TF */
+ .bltf = {
+ {
+ {57, 65, 73, 82},
+ {92, 103, 114, 125},
+ {138, 150, 164, 178},
+ {193, 208, 224, 241},
+ },
+ },
+ /* Default LUT */
+ .lut = {
+ {
+ {255, 255, 255},
+ {199, 199, 199},
+ {153, 153, 153},
+ {116, 116, 116},
+ {85, 85, 85},
+ {59, 59, 59},
+ {36, 36, 36},
+ {17, 17, 17},
+ {0, 0, 0},
+ },
+ },
+ .sd_brightness = &sd_brightness,
+ .use_vpulse2 = true,
+};
+
static tegra_dc_bl_output dsi_p_wuxga_10_1_bl_output_measured = {
0, 0, 1, 2, 3, 4, 5, 6,
7, 8, 9, 9, 10, 11, 12, 13,
@@ -677,6 +726,7 @@ static void dsi_p_wuxga_10_1_fb_data_init(struct tegra_fb_data *fb)
static void
dsi_p_wuxga_10_1_sd_settings_init(struct tegra_dc_sd_settings *settings)
{
+ *settings = dsi_p_wuxga_10_1_sd_settings;
settings->bl_device_name = "pwm-backlight";
}