diff options
| author | Adam Jiang <chaoj@nvidia.com> | 2011-11-17 13:09:04 +0900 |
|---|---|---|
| committer | Rohan Somvanshi <rsomvanshi@nvidia.com> | 2012-01-10 08:14:57 -0800 |
| commit | e63d69c493e0c0cc5f0f81fd09381e61178964d3 (patch) | |
| tree | 8630465b0a23568651f2a458cc24c7da46e70b55 /arch/arm/mach-tegra/pinmux-t3-tables.c | |
| parent | af30d3a3d056b8433eb4097070b4fbbc951f74ce (diff) | |
Tegra: Pinmux: Fixed up errors about DTV interface
Pin configuration on DTV interface could be enabled by this patch.
Fixed Bug 904626
Fixed Bug 881303
Change-Id: I6b5dc12629740bb8275156df9d9a5b4ca9dae352
Signed-off-by: Adam Jiang <chaoj@nvidia.com>
Reviewed-on: http://git-master/r/66626
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
(cherry picked from commit c34733e5ea933b322cd5edbceb93f921ffe413de)
Reviewed-on: http://git-master/r/73955
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/pinmux-t3-tables.c')
| -rw-r--r-- | arch/arm/mach-tegra/pinmux-t3-tables.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/mach-tegra/pinmux-t3-tables.c b/arch/arm/mach-tegra/pinmux-t3-tables.c index aaf1390933ed..51ec9a2873b4 100644 --- a/arch/arm/mach-tegra/pinmux-t3-tables.c +++ b/arch/arm/mach-tegra/pinmux-t3-tables.c @@ -257,7 +257,7 @@ const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE PINGROUP(GMI_WAIT, PI7, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31c8),\ PINGROUP(GMI_ADV_N, PK0, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31cc),\ PINGROUP(GMI_CLK, PK1, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31d0),\ - PINGROUP(GMI_CS0_N, PJ0, GMI, RSVD1, NAND, GMI, INVALID, RSVD, INPUT, 0x31d4),\ + PINGROUP(GMI_CS0_N, PJ0, GMI, RSVD1, NAND, GMI, DTV, RSVD, INPUT, 0x31d4),\ PINGROUP(GMI_CS1_N, PJ2, GMI, RSVD1, NAND, GMI, DTV, RSVD, INPUT, 0x31d8),\ PINGROUP(GMI_CS2_N, PK3, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x31dc),\ PINGROUP(GMI_CS3_N, PK4, GMI, RSVD1, NAND, GMI, GMI_ALT, RSVD, INPUT, 0x31e0),\ @@ -281,8 +281,8 @@ const struct tegra_drive_pingroup_desc tegra_soc_drive_pingroups[TEGRA_MAX_DRIVE PINGROUP(GMI_AD14, PH6, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x3228),\ PINGROUP(GMI_AD15, PH7, GMI, RSVD1, NAND, GMI, RSVD2, RSVD, INPUT, 0x322c),\ PINGROUP(GMI_A16, PJ7, GMI, UARTD, SPI4, GMI, GMI_ALT, RSVD, INPUT, 0x3230),\ - PINGROUP(GMI_A17, PB0, GMI, UARTD, SPI4, GMI, INVALID, RSVD, INPUT, 0x3234),\ - PINGROUP(GMI_A18, PB1, GMI, UARTD, SPI4, GMI, INVALID, RSVD, INPUT, 0x3238),\ + PINGROUP(GMI_A17, PB0, GMI, UARTD, SPI4, GMI, DTV, RSVD, INPUT, 0x3234),\ + PINGROUP(GMI_A18, PB1, GMI, UARTD, SPI4, GMI, DTV, RSVD, INPUT, 0x3238),\ PINGROUP(GMI_A19, PK7, GMI, UARTD, SPI4, GMI, RSVD3, RSVD, INPUT, 0x323c),\ PINGROUP(GMI_WR_N, PI0, GMI, RSVD1, NAND, GMI, RSVD3, RSVD, INPUT, 0x3240),\ PINGROUP(GMI_OE_N, PI1, GMI, RSVD1, NAND, GMI, RSVD3, RSVD, INPUT, 0x3244),\ |