summaryrefslogtreecommitdiff
path: root/arch/arm/mach-tegra/platsmp.c
diff options
context:
space:
mode:
authorPeng Du <pdu@nvidia.com>2013-01-18 15:13:51 -0800
committerTom Cherry <tcherry@nvidia.com>2014-01-21 15:13:49 -0800
commit96fa97ae333b544188b7c02a766ce37d99d894e5 (patch)
tree790ca2ed4611428f3edd9f1164c20b4146d3fc24 /arch/arm/mach-tegra/platsmp.c
parente55c04cc40f064d80c6a04328472db09a33c04dc (diff)
ARM: tegra: port inline assemblies for ARM64
Port the inline assemblies w.r.t ARMv8 ISA and #ifdef the code with CONFIG_ARM64. Change-Id: I430b441cc23c88ef947ddb7c5aa1836d06dbabf9 Signed-off-by: Peng Du <pdu@nvidia.com> Reviewed-on: http://git-master/r/196609 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/platsmp.c')
-rw-r--r--arch/arm/mach-tegra/platsmp.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 209c92ca7bc5..189a7b03d213 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -93,11 +93,20 @@ static void __init setup_core_count(void)
}
cpuid = (read_cpuid_id() >> 4) & 0xFFF;
+#ifdef CONFIG_ARM64
+ /* Denver ASIM? */
+ if (cpuid == 0xE0F) {
+ /* 30th bit of MPIDR_EL1: 0 => SMP, 1 => UP */
+ __asm__("mrs %0, mpidr_el1\n" : "=r" (l2ctlr));
+ number_of_cores = (l2ctlr & (1 << 30)) ? 2 : 1;
+ }
+#else
/* Cortex-A15? */
if (cpuid == 0xC0F) {
__asm__("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr));
number_of_cores = ((l2ctlr >> 24) & 3) + 1;
}
+#endif
else {
#endif
#ifdef CONFIG_HAVE_ARM_SCU