diff options
| author | Scott Williams <scwilliams@nvidia.com> | 2011-07-21 16:06:08 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:46:57 -0800 |
| commit | 6031a0cd1a2391a30e30a5edbcaccf5a1868969c (patch) | |
| tree | 46b2c748f1bce772217468b3cbae1295c7d002e2 /arch/arm/mach-tegra/platsmp.c | |
| parent | 235b7a5f627819f05e538caf5f21220b8450ec73 (diff) | |
ARM: tegra3: power: Add LP2 power mode support for CPU 0
Add support for forced Tegra3 LP2 low power mode on the boot processor
(CPU 0) via the cluster control interface when all others are offline.
Switching to the LP CPU mode is also enabled with this change.
LP2 in idle and LP2 mode on the secondary processors is not yet
supported.
Change-Id: Icb898729f093be5e006c413f701532dd45228687
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Rebase-Id: Rd5d8c2b0addfd6853033670b992ae082e4a0d9c8
Diffstat (limited to 'arch/arm/mach-tegra/platsmp.c')
| -rw-r--r-- | arch/arm/mach-tegra/platsmp.c | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index a7b81919ba90..6cd9c61b68e9 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c @@ -49,17 +49,12 @@ const struct cpumask *const tegra_cpu_init_mask = to_cpumask(tegra_cpu_init_bits #define CPU_CLOCK(cpu) (0x1<<(8+cpu)) #define CPU_RESET(cpu) (0x1111ul<<(cpu)) -#ifdef CONFIG_ARCH_TEGRA_2x_SOC -/* For Tegra2 use the software-written value of the reset register for status.*/ -#define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET -#else +#ifndef CONFIG_ARCH_TEGRA_2x_SOC #define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR \ (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x34c) #define CAR_BOND_OUT_V \ (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x390) #define CAR_BOND_OUT_V_CPU_G (1<<0) -#define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS \ - (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x470) #endif static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE); |