diff options
| author | Mohan T <mohant@nvidia.com> | 2014-01-03 00:39:18 +0530 |
|---|---|---|
| committer | Bitan Biswas <bbiswas@nvidia.com> | 2014-01-03 11:24:12 -0800 |
| commit | e41d9838c8b4a2b269b376a3e20330c07cac391e (patch) | |
| tree | f4557888726cce79f065d1cba9cb8bf7a45f2db9 /arch/arm/mach-tegra/pm.c | |
| parent | f4a063081552617e72cbdda5596ae7bd537696f7 (diff) | |
ARM: tegra: pinmux: correct pinmux resume sequence
Do not operate on DPD pads and do not TRISTATE
pins before restoring for T124
Bug 1416263
Bug 1429819
Change-Id: I7261c7e5d4341f6d74dadf1ab6af985e7965b860
Signed-off-by: Mohan T <mohant@nvidia.com>
Reviewed-on: http://git-master/r/351369
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/pm.c')
| -rw-r--r-- | arch/arm/mach-tegra/pm.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index d8cf8c299a0a..e6c0cbb56370 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -3,7 +3,7 @@ * * CPU complex suspend & resume functions for Tegra SoCs * - * Copyright (c) 2009-2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2009-2014, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -149,6 +149,8 @@ extern int tegra_smmu_resume(struct device *dev); extern int tegra_smmu_suspend(struct device *dev); #endif +bool tegra_is_dpd_mode; + #define TEGRA_POWER_PWRREQ_POLARITY (1 << 8) /* core power request polarity */ #define TEGRA_POWER_PWRREQ_OE (1 << 9) /* core power request enable */ #define TEGRA_POWER_SYSCLK_POLARITY (1 << 10) /* sys clk polarity */ @@ -1065,6 +1067,7 @@ static void tegra_pm_set(enum tegra_suspend_mode mode) #if !defined(CONFIG_ARCH_TEGRA_3x_SOC) && !defined(CONFIG_ARCH_TEGRA_2x_SOC) #if defined(CONFIG_ARCH_TEGRA_11x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC) writel(0x800fdfff, pmc + PMC_IO_DPD_REQ); + tegra_is_dpd_mode = true; #else writel(0x800fffff, pmc + PMC_IO_DPD_REQ); #endif |