diff options
| author | Alex Frid <afrid@nvidia.com> | 2012-02-05 00:12:59 -0800 |
|---|---|---|
| committer | Lokesh Pathak <lpathak@nvidia.com> | 2012-02-23 22:40:23 -0800 |
| commit | 3e39a36eb51fb4f755bf9d3229e91c3a58663b97 (patch) | |
| tree | f51d0d55c248c3f8514e79606cff9e08ff582c72 /arch/arm/mach-tegra/pm.c | |
| parent | 199850ff2eec72260d84768e273c808ccc068b4c (diff) | |
ARM: tegra: clock: Update secondary pll dividers resume
During resume from LP0 on Tegra3 always enable pll secondary dividers
before clocks restoration (to make sure clock sources are enabled).
Restore actual secondary dividers settings after clocks are restored.
Remove pllp secondary dividers restoration from cpu complex restore,
and add them to common clock restoration procedure. These dividers
are not affected by CPU complex suspend, only by LP0 core suspend.
Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 1f631436717c0602ef30770f7976615150114afe)
Change-Id: I45777ca0535f51a39c35e9d360ac6e97a13ea92c
Reviewed-on: http://git-master/r/84712
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/pm.c')
| -rw-r--r-- | arch/arm/mach-tegra/pm.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index bd0775328d75..e37efe92cbae 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -372,9 +372,9 @@ static void restore_cpu_complex(u32 mode) #ifdef CONFIG_ARCH_TEGRA_2x_SOC writel(tegra_sctx.pllp_misc, clk_rst + CLK_RESET_PLLP_MISC); writel(tegra_sctx.pllp_base, clk_rst + CLK_RESET_PLLP_BASE); -#endif writel(tegra_sctx.pllp_outa, clk_rst + CLK_RESET_PLLP_OUTA); writel(tegra_sctx.pllp_outb, clk_rst + CLK_RESET_PLLP_OUTB); +#endif /* Is CPU complex already running on PLLX? */ reg = readl(clk_rst + CLK_RESET_CCLK_BURST); |