diff options
| author | Jin Qian <jqian@nvidia.com> | 2011-09-02 16:22:18 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:48:51 -0800 |
| commit | 74f4bf89013bd5b955c77dd30c13e1879889db6c (patch) | |
| tree | b18736e38dfbfd55b7cd5abec448db82aa489b8b /arch/arm/mach-tegra/pm.c | |
| parent | 514c27412c673913e7555368ef2ddec82737ebd5 (diff) | |
ARM: tegra: power: save cluster switch status before entering LP0
warm boot reads SCRATCH4 to choose wake-up from LP or G
Bug 862504
Change-Id: I5ee4697c6268d379a6708e6a87e3f7df12f2994a
Reviewed-on: http://git-master/r/50610
Reviewed-by: Jin Qian <jqian@nvidia.com>
Tested-by: Jin Qian <jqian@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: R7e61acb99f023449c2416054c44b75837c3aff94
Diffstat (limited to 'arch/arm/mach-tegra/pm.c')
| -rw-r--r-- | arch/arm/mach-tegra/pm.c | 19 |
1 files changed, 16 insertions, 3 deletions
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index 0a4de1a68b5c..a3fb3c08f1cc 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -133,10 +133,15 @@ struct suspend_context tegra_sctx; #define PMC_COREPWRGOOD_TIMER 0x3c #define PMC_SCRATCH0 0x50 #define PMC_SCRATCH1 0x54 +#define PMC_SCRATCH4 0x60 #define PMC_CPUPWRGOOD_TIMER 0xc8 #define PMC_CPUPWROFF_TIMER 0xcc #define PMC_COREPWROFF_TIMER PMC_WAKE_DELAY +#ifdef CONFIG_TEGRA_CLUSTER_CONTROL +#define PMC_SCRATCH4_WAKE_CLUSTER_MASK (1<<31) +#endif + #define CLK_RESET_CCLK_BURST 0x20 #define CLK_RESET_CCLK_DIVIDER 0x24 #define CLK_RESET_PLLC_BASE 0x80 @@ -770,15 +775,23 @@ int tegra_suspend_dram(enum tegra_suspend_mode mode, unsigned int flags) cpu_complex_pm_enter(); if (mode == TEGRA_SUSPEND_LP0) { +#ifdef CONFIG_TEGRA_CLUSTER_CONTROL + u32 reg = readl(pmc + PMC_SCRATCH4); + if (is_lp_cluster()) + reg |= PMC_SCRATCH4_WAKE_CLUSTER_MASK; + else + reg &= (~PMC_SCRATCH4_WAKE_CLUSTER_MASK); + pmc_32kwritel(reg, PMC_SCRATCH4); +#endif tegra_lp0_suspend_mc(); tegra_cpu_reset_handler_save(); + } + else if (mode == TEGRA_SUSPEND_LP1) + *iram_cpu_lp1_mask = 1; suspend_cpu_complex(flags); - if (mode == TEGRA_SUSPEND_LP1) - *iram_cpu_lp1_mask = 1; - flush_cache_all(); outer_flush_all(); outer_disable(); |