diff options
| author | Bo Yan <byan@nvidia.com> | 2012-10-08 19:52:49 -0700 |
|---|---|---|
| committer | Simone Willett <swillett@nvidia.com> | 2012-10-22 18:40:42 -0700 |
| commit | 8102489b88be4b50b418e3854f019127b10a983b (patch) | |
| tree | f5aa1e982ebaf805029e3b7b13db055fd0074e8f /arch/arm/mach-tegra/pm.c | |
| parent | e13bb063566804a55a8e0ed7181410f78952a075 (diff) | |
ARM: tegra11x: CPU start up fix
The first time when a CPU powers up in kernel, it has to be
done by directly toggling PMC register.
Subsequent CPU power up sequence is controlled by flow controller.
This is done after LP0 exit as well.
Signed-off-by: Bo Yan <byan@nvidia.com>
Reviewed-on: http://git-master/r/143296
Change-Id: If32712706d827e4d0337d75163449cfa0a3a50f8
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/146484
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>
Tested-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Diffstat (limited to 'arch/arm/mach-tegra/pm.c')
| -rw-r--r-- | arch/arm/mach-tegra/pm.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index 22d9095b1b1c..5c1e96e367f6 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -941,6 +941,7 @@ int tegra_suspend_dram(enum tegra_suspend_mode mode, unsigned int flags) tegra_lp0_suspend_mc(); tegra_cpu_reset_handler_save(); tegra_tsc_wait_for_suspend(); + tegra_smp_clear_power_mask(); } else if (mode == TEGRA_SUSPEND_LP1) *iram_cpu_lp1_mask = 1; |