diff options
| author | Alex Frid <afrid@nvidia.com> | 2012-09-04 15:42:28 -0700 |
|---|---|---|
| committer | Varun Colbert <vcolbert@nvidia.com> | 2012-09-11 11:13:44 -0700 |
| commit | ff4865e3cab44075aea3e7d9e9cad6e0be09301f (patch) | |
| tree | 8973901b96f8d1d49ed306324972d778094b3f80 /arch/arm/mach-tegra/pm.c | |
| parent | cb6b1f7094366fe0a7dbe3bde0f0a3fcc6478b0a (diff) | |
ARM: tegra11: clock: Modify pllx and cpu burst policy restore
Removed PLLX and cpu burst policy restoration on Tegra11 from
restore_cpu_complex() routine. These settings are preserved across
cpu complex rail-gating, and should be restored by common clock
suspend/resume code across core rail-gating (LP0 state).
Added PLLX restoration to common clock resume procedure (was missing,
since it was done in restore_cpu_complex()). Fixed cpu burst policy
restoration for LP CPU to make sure PLLX DIV2 bypass is not changing
while PLLX is used as cpu clock source.
Change-Id: I3425a4ad65c51d9485e1c3240905b3ce3066e74c
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/130856
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/pm.c')
| -rw-r--r-- | arch/arm/mach-tegra/pm.c | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index 8621789c31e3..ef14621b2f5c 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c @@ -320,13 +320,23 @@ static void set_power_timers(unsigned long us_on, unsigned long us_off, static void restore_cpu_complex(u32 mode) { int cpu = smp_processor_id(); - unsigned int reg, policy; + unsigned int reg; +#if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC) + unsigned int policy; +#endif BUG_ON(cpu != 0); #ifdef CONFIG_SMP cpu = cpu_logical_map(cpu); #endif + +/* + * On Tegra11x PLLX and CPU burst policy is either preserved across LP2, + * or restored by common clock suspend/resume procedures. Hence, we don't + * need it here. + */ +#if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC) /* Is CPU complex already running on PLLX? */ reg = readl(clk_rst + CLK_RESET_CCLK_BURST); policy = (reg >> CLK_RESET_CCLK_BURST_POLICY_SHIFT) & 0xF; @@ -370,7 +380,7 @@ static void restore_cpu_complex(u32 mode) writel(tegra_sctx.cpu_burst, clk_rst + CLK_RESET_CCLK_BURST); } - +#endif writel(tegra_sctx.clk_csite_src, clk_rst + CLK_RESET_SOURCE_CSITE); /* Do not power-gate CPU 0 when flow controlled */ |