diff options
| author | Joseph Lo <josephl@nvidia.com> | 2013-07-03 17:50:37 +0800 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2013-07-19 10:08:04 -0600 |
| commit | c04c77540a4f996ee94d0240bbae3a7512febd37 (patch) | |
| tree | a480639fb642cb10b9bf738f294f68ed40e99b5c /arch/arm/mach-tegra/reset-handler.S | |
| parent | 3045cb33eb6081a937d9a2873f5fb88d9fcb7900 (diff) | |
ARM: tegra: do v7_invalidate_l1 only when CPU is Cortex-A9
The v7_invalidate_l1 was used for the L1 cache that come out from reset
in a undefined state. This is no need for Cortex-A15. We do it for A9
only.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/reset-handler.S')
| -rw-r--r-- | arch/arm/mach-tegra/reset-handler.S | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S index 39dc9e7834f3..75285a3b816e 100644 --- a/arch/arm/mach-tegra/reset-handler.S +++ b/arch/arm/mach-tegra/reset-handler.S @@ -40,9 +40,11 @@ * re-enabling sdram. * * r6: SoC ID + * r8: CPU part number */ ENTRY(tegra_resume) - bl v7_invalidate_l1 + check_cpu_part_num 0xc09, r8, r9 + bleq v7_invalidate_l1 cpu_id r0 tegra_get_soc_id TEGRA_APB_MISC_BASE, r6 @@ -70,7 +72,8 @@ no_cpu0_chk: str r1, [r2] 1: - check_cpu_part_num 0xc09, r8, r9 + mov32 r9, 0xc09 + cmp r8, r9 bne not_ca9 #ifdef CONFIG_HAVE_ARM_SCU /* enable SCU */ |