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| author | Peng Du <pdu@nvidia.com> | 2013-08-14 20:08:20 -0700 |
|---|---|---|
| committer | Tom Cherry <tcherry@nvidia.com> | 2014-01-21 15:13:49 -0800 |
| commit | e55c04cc40f064d80c6a04328472db09a33c04dc (patch) | |
| tree | b70444d9887b7e418b5bc2e0e62f0843596f0e16 /arch/arm/mach-tegra/reset.c | |
| parent | 9f70555af89012cd8f105a484efdba5a3594510b (diff) | |
ARM: tegra: fix arch header includes for ARM64
Change-Id: Iec07f74b6c84dfabc68c8a10c91022b9ae51d9c1
Signed-off-by: Peng Du <pdu@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/reset.c')
| -rw-r--r-- | arch/arm/mach-tegra/reset.c | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c index fbec87eec053..85dcbdf1cf4d 100644 --- a/arch/arm/mach-tegra/reset.c +++ b/arch/arm/mach-tegra/reset.c @@ -114,13 +114,19 @@ void __init tegra_cpu_reset_handler_init(void) virt_to_phys((void *)tegra_resume); #endif +#ifdef CONFIG_ARM64 + flush_icache_range( + (unsigned long)&__tegra_cpu_reset_handler_data[0], + (unsigned long)&__tegra_cpu_reset_handler_data[TEGRA_RESET_DATA_SIZE]); +#else /* Push all of reset handler data out to the L3 memory system. */ __cpuc_coherent_kern_range( - (unsigned long)&__tegra_cpu_reset_handler_data[0], - (unsigned long)&__tegra_cpu_reset_handler_data[TEGRA_RESET_DATA_SIZE]); + (unsigned long)&__tegra_cpu_reset_handler_data[0], + (unsigned long)&__tegra_cpu_reset_handler_data[TEGRA_RESET_DATA_SIZE]); outer_clean_range(__pa(&__tegra_cpu_reset_handler_data[0]), - __pa(&__tegra_cpu_reset_handler_data[TEGRA_RESET_DATA_SIZE])); + __pa(&__tegra_cpu_reset_handler_data[TEGRA_RESET_DATA_SIZE])); +#endif if (!tegra_cpu_is_dsim()) /* Can't write IRAM on DSIM/MTS (yet) */ tegra_cpu_reset_handler_enable(); |