diff options
| author | Prashant Gaikwad <pgaikwad@nvidia.com> | 2011-12-01 10:17:51 +0530 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2011-12-15 11:53:57 +0530 |
| commit | e73d060b94d42ce0ab731e159070bfb778895aa1 (patch) | |
| tree | 5f2d43373fad5e1442667420cc6439a01695df6b /arch/arm/mach-tegra/sleep-t2.S | |
| parent | 558ab146ff15c86c1d5383a1b63479fc856e1115 (diff) | |
arm: tegra: Invalidate TLB/BTAC afer enabling coherency
Change-Id: Idaf841e245f3bccaae77375bb839e8c00bbc7542
Reviewed-on: http://git-master/r/67592
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/sleep-t2.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep-t2.S | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/sleep-t2.S b/arch/arm/mach-tegra/sleep-t2.S index d350a17f475f..01791439426b 100644 --- a/arch/arm/mach-tegra/sleep-t2.S +++ b/arch/arm/mach-tegra/sleep-t2.S @@ -240,7 +240,7 @@ ENTRY(tegra2_sleep_wfi) #else mcr p15, 0, r11, c1, c0, 1 @ reenable coherency - +#endif /* Invalidate the TLBs & BTAC */ mov r1, #0 mcr p15, 0, r1, c8, c3, 0 @ invalidate shared TLBs @@ -256,7 +256,6 @@ ENTRY(tegra2_sleep_wfi) #else bl __cpuc_flush_kern_all #endif -#endif #ifdef CONFIG_CACHE_L2X0 /* Issue a PL310 cache sync operation */ |