diff options
| author | Antti P Miettinen <amiettinen@nvidia.com> | 2012-10-03 13:37:15 +0300 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 13:02:55 -0700 |
| commit | 1ac02079fb6e0ff5de5bcbe45aa5e26483555e52 (patch) | |
| tree | 086261f06eadd095ceab360365f5e2c7418a807a /arch/arm/mach-tegra/sleep-t20.S | |
| parent | 87393363e6f154dc2eac71551c259fc3d49b58ce (diff) | |
ARM: Tegra: Keep L2 available while MMU is on
As page tables can be outer cacheable we want to keep L2
available while MMU is on. Therefore, upon resuming from power
gating, enable L2 before MMU enable and upon power gating entry
disable L2 after MMU has been disabled. The optimization
is not stable with secure OS so leave the optimization out
for secure OS config. T148 has separate caches so there L2 flush
cannot be avoided. Also the caches are of different size so
the l2x0 module is initialized upon resume.
Bug 1046695
Change-Id: I520db89e880c08113e0b3e29a88efaad0c100045
Signed-off-by: Antti P Miettinen <amiettinen@nvidia.com>
Reviewed-on: http://git-master/r/204852
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/sleep-t20.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep-t20.S | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/sleep-t20.S b/arch/arm/mach-tegra/sleep-t20.S index b189e573ecdb..ca540dd51599 100644 --- a/arch/arm/mach-tegra/sleep-t20.S +++ b/arch/arm/mach-tegra/sleep-t20.S @@ -177,6 +177,7 @@ ENTRY(tegra2_sleep_core_finish) sub r1, r1, r2 mov32 r2, TEGRA_IRAM_CODE_AREA add r1, r1, r2 + mov r11, #0 b tegra_turn_off_mmu ENDPROC(tegra2_sleep_core_finish) |