diff options
| author | Alex Frid <afrid@nvidia.com> | 2013-04-07 21:26:58 -0700 |
|---|---|---|
| committer | Mrutyunjay Sawant <msawant@nvidia.com> | 2013-04-09 05:19:25 -0700 |
| commit | a1dda2e1a966cdcb40fd7914b2e4dedd5c7a852e (patch) | |
| tree | 8fea9cce28a3ad0b61608065d8ff34542f056d3d /arch/arm/mach-tegra/sleep-t3.S | |
| parent | 7e5e5a7571d0a1f40a11e2407b8dcba8e6d4b59e (diff) | |
Revert "ARM: tegra: power: Disable pll secondary dividers in LP1"
This reverts commit a04ec5397d24ab57d5eed38727dc8a3963c8b71a.
Testing for integration of this commit to main showed LP1 problems -
safer to revert until root-caused.
Change-Id: Ibacd97b01dbb6950bc916b0b9e53b535e6013678
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/217174
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/sleep-t3.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep-t3.S | 35 |
1 files changed, 0 insertions, 35 deletions
diff --git a/arch/arm/mach-tegra/sleep-t3.S b/arch/arm/mach-tegra/sleep-t3.S index 0f11efd5da81..2bd64b2fa5cd 100644 --- a/arch/arm/mach-tegra/sleep-t3.S +++ b/arch/arm/mach-tegra/sleep-t3.S @@ -95,11 +95,8 @@ #define CLK_RESET_PLLX_MISC3_IDDQ 3 #endif -#define CLK_RESET_PLLC_OUT0 0x84 -#define CLK_RESET_PLLM_OUT0 0x94 #define CLK_RESET_PLLP_OUTA 0xa4 #define CLK_RESET_PLLP_OUTB 0xa8 -#define PLL_OUT_ENABLE 0x3 #define PMC_PLLP_WB0_OVERRIDE 0xf8 #define PMC_PLLM_WB0_OVERRIDE 0x1dc @@ -418,23 +415,6 @@ ENTRY(tegra3_lp1_reset) add r1, r1, #LOCK_DELAY wait_until r1, r7, r3 - /* after PLLs are locked enable secondary dividers */ - ldr r1, [r0, #CLK_RESET_PLLM_OUT0] - orr r1, #PLL_OUT_ENABLE - str r1, [r0, #CLK_RESET_PLLM_OUT0] - ldr r1, [r0, #CLK_RESET_PLLC_OUT0] - orr r1, #PLL_OUT_ENABLE - str r1, [r0, #CLK_RESET_PLLC_OUT0] - - ldr r1, [r0, #CLK_RESET_PLLP_OUTA] - orr r1, #PLL_OUT_ENABLE - orr r1, #(PLL_OUT_ENABLE << 16) - str r1, [r0, #CLK_RESET_PLLP_OUTA] - ldr r1, [r0, #CLK_RESET_PLLP_OUTB] - orr r1, #PLL_OUT_ENABLE - orr r1, #(PLL_OUT_ENABLE << 16) - str r1, [r0, #CLK_RESET_PLLP_OUTB] - #if defined(CONFIG_ARCH_TEGRA_3x_SOC) add r5, pc, #tegra3_sdram_pad_save-(.+8) @ r5 --> saved data #endif @@ -855,9 +835,6 @@ lp1_volt_skip: wait_until r1, r7, r9 /* disable PLLM via PMC in LP1 */ - ldr r0, [r5, #CLK_RESET_PLLM_OUT0] - bic r0, #PLL_OUT_ENABLE - str r0, [r5, #CLK_RESET_PLLM_OUT0] ldr r0, [r4, #PMC_PLLP_WB0_OVERRIDE] bic r0, r0, #(1 << 12) str r0, [r4, #PMC_PLLP_WB0_OVERRIDE] @@ -868,15 +845,6 @@ powerdown_pll_pcx: tst r11, #TEGRA_POWER_LP1_AUDIO @ check if voice call is going on bne powerdown_pll_cx @ if yes, do not turn off pll-p/pll-a - ldr r0, [r5, #CLK_RESET_PLLP_OUTA] - bic r0, #PLL_OUT_ENABLE - bic r0, #(PLL_OUT_ENABLE << 16) - str r0, [r5, #CLK_RESET_PLLP_OUTA] - ldr r0, [r5, #CLK_RESET_PLLP_OUTB] - bic r0, #PLL_OUT_ENABLE - bic r0, #(PLL_OUT_ENABLE << 16) - str r0, [r5, #CLK_RESET_PLLP_OUTB] - ldr r0, [r5, #CLK_RESET_PLLP_BASE] bic r0, r0, #(1<<30) str r0, [r5, #CLK_RESET_PLLP_BASE] @@ -885,9 +853,6 @@ powerdown_pll_pcx: str r0, [r5, #CLK_RESET_PLLA_BASE] powerdown_pll_cx: - ldr r0, [r5, #CLK_RESET_PLLC_OUT0] - bic r0, #PLL_OUT_ENABLE - str r0, [r5, #CLK_RESET_PLLC_OUT0] ldr r0, [r5, #CLK_RESET_PLLC_BASE] bic r0, r0, #(1<<30) str r0, [r5, #CLK_RESET_PLLC_BASE] |