diff options
| author | Karthik Ramakrishnan <karthikr@nvidia.com> | 2013-06-06 16:32:55 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 13:17:29 -0700 |
| commit | 544ff9e39c40f9dcfae29b5675a82e4eec56545d (patch) | |
| tree | e27361c98619020bc6541f0950db0e4f3af2e894 /arch/arm/mach-tegra/sleep-t30.S | |
| parent | cf32f46fc0256fd98d773738baf3ab0c00cae031 (diff) | |
arm: tegra: Fix incorrect register usage in lp1 suspend
The register r0 is being used as TEGRA_CLK_RESET_BASE
address, and r5 is used as tegra3_sdram_pad_save register.
These registers were used incorrectly here.
Bug 1270351
Change-Id: I9fe39ab052fa875e809d7b33a5ae346060d3090f
Signed-off-by: Karthik Ramakrishnan <karthikr@nvidia.com>
Reviewed-on: http://git-master/r/236472
Reviewed-by: Mrutyunjay Sawant <msawant@nvidia.com>
Tested-by: Mrutyunjay Sawant <msawant@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/sleep-t30.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep-t30.S | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm/mach-tegra/sleep-t30.S b/arch/arm/mach-tegra/sleep-t30.S index 416f025bb4cc..354c4476a5ff 100644 --- a/arch/arm/mach-tegra/sleep-t30.S +++ b/arch/arm/mach-tegra/sleep-t30.S @@ -511,11 +511,11 @@ lp1_voltset: wait_for_us r1, r7, r9 mov32 r3, 0x7D0 /* Wait for 2ms and try transaction again */ - add r0, r1, r3 + add r3, r1, r3 loop_i2c_status_resume: add r1, r1, #0xFA /* Check status every 250us */ wait_until r1, r7, r9 - cmp r0, r1 + cmp r3, r1 beq lp1_voltset ldr r3, [r4, #I2C_STATUS] @@ -524,8 +524,8 @@ loop_i2c_status_resume: lp1_voltskip_resume: /* Disable the DVC-I2C Controller */ - mov r0, #(1 << 15) - str r0, [r5, #CLK_RESET_CLK_ENB_H_CLR] + mov r1, #(1 << 15) + str r1, [r0, #CLK_RESET_CLK_ENB_H_CLR] #endif #if defined (CONFIG_CACHE_L2X0) |