diff options
| author | Alex Waterman <alexw@nvidia.com> | 2013-07-31 15:13:22 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 13:38:48 -0700 |
| commit | 2229e6d8f7e79a3781c77d14d2c0a5fc831afa87 (patch) | |
| tree | 93fdba497f0cf2a7d098ff297db952cf6c22fd7d /arch/arm/mach-tegra/sleep-t30.S | |
| parent | 270b070d98b6cd528f28f953bcb29d378cc626da (diff) | |
ARM: tegra14: BGBIAS cells cannot be in DPD when entering LP0
For low frequencies that use Schmitt mode triggering in the EMC the
BGBIAS cells are not needed and can be turned off. However, if the
system is at a low frequency and goes into LP0 (i.e when the BBC is
in airplane mode) the bootrom will fail to read memory on wake up.
This occurs because the bootrom boots at the max EMC frequency (787
or 921 MHz) which requires the BGBIAS cells to be alive.
To fix the problem the BGBIAS cells are taken out of DPD when the
system goes into LP0.
Bug 1332120
Reviewed-on: http://git-master/r/256523
(cherry picked from commit e59834d3649eb0e022d0d9cadc2a172c5b43e519)
Change-Id: Iab8082f946c6094b65b1fd17fb162ff7553436fb
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/257648
Reviewed-by: Graziano Misuraca <gmisuraca@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/sleep-t30.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep-t30.S | 21 |
1 files changed, 17 insertions, 4 deletions
diff --git a/arch/arm/mach-tegra/sleep-t30.S b/arch/arm/mach-tegra/sleep-t30.S index 40365916dd32..99ddde428d15 100644 --- a/arch/arm/mach-tegra/sleep-t30.S +++ b/arch/arm/mach-tegra/sleep-t30.S @@ -63,8 +63,11 @@ #define PMC_IO_DPD_REQ 0x1b8 #define PMC_IO_DPD_STATUS 0x1bc -#define PMC_SCRATCH1_ECO 0x264 -#define PMC_POR_DPD_CTRL 0x264 +#define PMC_IO_DPD2_REQ 0x1c0 +#define PMC_IO_DPD2_REQ_CODE_DPD_OFF (1 << 30) +#define PMC_IO_DPD2_REQ_DISC_BIAS (1 << 27) +#define PMC_SCRATCH1_ECO 0x264 +#define PMC_POR_DPD_CTRL 0x264 #define FLOW_IPC_STS 0x500 #define FLOW_IPC_STS_AP2BB_MSC_STS_0 (1 << 4) @@ -1285,10 +1288,20 @@ defined(CONFIG_ARCH_TEGRA_14x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC) bne pmc_io_dpd_skip mov32 r1, 0x8EC00000 str r1, [r4, #PMC_IO_DPD_REQ] -pmc_io_dpd_skip: - dsb + mov pc, lr +pmc_io_dpd_skip: +#if defined(CONFIG_ARCH_TEGRA_14x_SOC) + /* + * Make sure the BGBIAS pads are not in DPD so that when the system + * comes out of LP0 at max EMC frequency we can read memory. + */ + ldr r1, =PMC_IO_DPD2_REQ_CODE_DPD_OFF + orr r1, r1, #PMC_IO_DPD2_REQ_DISC_BIAS + str r1, [r4, #PMC_IO_DPD2_REQ] +#endif + dsb mov pc, lr .ltorg |