diff options
| author | Jeetesh Burman <jburman@nvidia.com> | 2014-02-04 17:09:11 +0530 |
|---|---|---|
| committer | Bharat Nihalani <bnihalani@nvidia.com> | 2014-02-10 22:44:40 -0800 |
| commit | 000aa289f8789540082ed61a1101bbcbd420a19e (patch) | |
| tree | f0a3e170b55ee61651d64147c11caf8ea713f530 /arch/arm/mach-tegra/sleep-t30.S | |
| parent | 5c1ed6e85597f148def3cd4ccd0aa560ad53e0b3 (diff) | |
arm: tegra: program DDR IO DPD reg for T124
Bug 1448470
Change-Id: I35b94c3c5e7e29b12f10b64d56b7077f8f452c88
Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
Reviewed-on: http://git-master/r/363239
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Pankaj Dabade <pdabade@nvidia.com>
Tested-by: Pankaj Dabade <pdabade@nvidia.com>
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/sleep-t30.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep-t30.S | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/sleep-t30.S b/arch/arm/mach-tegra/sleep-t30.S index 98e836ca8f3a..a36cd5a16a03 100644 --- a/arch/arm/mach-tegra/sleep-t30.S +++ b/arch/arm/mach-tegra/sleep-t30.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -68,12 +68,15 @@ #define PMC_IO_DPD2_REQ_DISC_BIAS (1 << 27) #define PMC_SCRATCH1_ECO 0x264 #define PMC_POR_DPD_CTRL 0x264 + +#if defined(CONFIG_ARCH_TEGRA_12x_SOC) #define PMC_IO_DPD3_REQ 0x45c #define PMC_IO_DPD3_STATUS 0x460 #define EMC_SEL_DPD_CTRL 0x3d8 #define PMC_POR_DPD_CTRL 0x264 +#endif #define FLOW_IPC_STS 0x500 #define FLOW_IPC_STS_AP2BB_MSC_STS_0 (1 << 4) @@ -1411,13 +1414,14 @@ defined(CONFIG_ARCH_TEGRA_14x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC) mov32 r0, TEGRA_EMC0_BASE @ r0 reserved for emc base #endif enter_self_refresh: +#if defined(CONFIG_ARCH_TEGRA_12x_SOC) /* Enable SEL_DPD */ ldr r1, [r0, #EMC_SEL_DPD_CTRL] orr r1, r1, #0xF orr r1, r1, #0xF0 orr r1, r1, #0x100 str r1, [r0, #EMC_SEL_DPD_CTRL] - +#endif mov r1, #0 str r1, [r0, #EMC_ZCAL_INTERVAL] str r1, [r0, #EMC_AUTO_CAL_INTERVAL] @@ -1486,9 +1490,11 @@ defined(CONFIG_ARCH_TEGRA_14x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC) tst r1, #PMC_CTRL_SIDE_EFFECT_LP0 bne pmc_io_dpd_skip +#if defined(CONFIG_ARCH_TEGRA_12x_SOC) ldr r1, [r4, #PMC_POR_DPD_CTRL] orr r1, r1, #0x80000003 str r1, [r4, #PMC_POR_DPD_CTRL] +#endif #if !defined(CONFIG_ARCH_TEGRA_12x_SOC) mov32 r1, 0x8EC00000 |