diff options
| author | Prashant Malani <pmalani@nvidia.com> | 2013-04-01 16:12:04 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2013-09-14 13:24:48 -0700 |
| commit | 15acabfe0ee49d0a290c267e56640913abff2c1b (patch) | |
| tree | 9ed03f82aa6a447e6858a02c01fc938c17882214 /arch/arm/mach-tegra/sleep.S | |
| parent | b56d76a07306d58065d754456cb0bc809471bd4f (diff) | |
ARM: tegra: Add LPAE support for suspend pgtable
LPAE allows physical addresses upto 40 bits.
Consequently, the layout of TTBR changes. This
change modifies the suspend pgtable init and
suspend code to support the increased address
range and register layout for LPAE.
Bug 1271462
Change-Id: I44015aba943e2972cc99559d957209a7d1c364c7
Signed-off-by: Prashant Malani <pmalani@nvidia.com>
Reviewed-on: http://git-master/r/215252
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alexander Van Brunt <avanbrunt@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/sleep.S')
| -rw-r--r-- | arch/arm/mach-tegra/sleep.S | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S index 7150c8470133..5e4b1473329f 100644 --- a/arch/arm/mach-tegra/sleep.S +++ b/arch/arm/mach-tegra/sleep.S @@ -242,6 +242,17 @@ ENTRY(tegra_turn_off_mmu) * change page table pointer to tegra_pgd_phys, so that IRAM * and MMU shut-off will be mapped virtual == physical */ +#if defined(CONFIG_ARM_LPAE) + mrrc p15, 0, r3, r8, c2 @ TTB 0 + ldr r2, tegra_pgd_phys_address + ldrd r2, r3, [r2] + bic r8, r8, #0xFF @ clear base_addr[40:32] from TTB 0 + orr r8, r8, r3 @ load new base_addr[40:32] into TTB 0 + mov r3, #0 + mcr p15, 0, r3, c13, c0, 1 @ reserved context + isb + mcrr p15, 0, r2, r8, c2 @ TTB 0 +#else mrc p15, 0, r2, c2, c0, 0 @ TTB 0 mov32 r3, ~PAGE_MASK and r2, r2, r3 @@ -252,6 +263,7 @@ ENTRY(tegra_turn_off_mmu) mcr p15, 0, r2, c13, c0, 1 @ reserved context isb mcr p15, 0, r3, c2, c0, 0 @ TTB 0 +#endif isb mcr p15, 0, r2, c8, c3, 0 @ invalidate TLB |