diff options
| author | Scott Williams <scwilliams@nvidia.com> | 2012-02-03 11:00:50 -0800 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2012-06-25 15:30:13 +0530 |
| commit | 61dad3377a86b0711073637ef3c0fcd95f44a3de (patch) | |
| tree | 46f8b4a856d63a89b4b2cde36c02672b53a049e7 /arch/arm/mach-tegra/sleep.h | |
| parent | 2995e97b2256f32438545f8f0e37415d83820496 (diff) | |
ARM: tegra: smp: Add support for Cortex-A15 boot_secondary
Cortex-A15 does not have a memory-mapped SCU in the PERIPHBASE
aperture. Instead, the number of CPUs present is obtained from
the architectural L2 Cache Control (L2CTLR) register.
Enable HAVE_ARM_SCU only on platforms that have a memory-mapped
SCU and add the necessary conditionals to prevent access to the
memory-mapped SCU address range on platforms that don't.
Change-Id: I4027d034fe79339fab0030a44780240785206cba
Signed-off-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-on: http://git-master/r/79341
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mark Stadler <mastadler@nvidia.com>
Reviewed-by: Jeff Smith <jsmith@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/sleep.h')
| -rw-r--r-- | arch/arm/mach-tegra/sleep.h | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h index 00bf616b4a88..a2f4712de3b0 100644 --- a/arch/arm/mach-tegra/sleep.h +++ b/arch/arm/mach-tegra/sleep.h @@ -85,8 +85,10 @@ #ifdef CONFIG_CACHE_L2X0 #define TEGRA_PL310_VIRT (TEGRA_ARM_PL310_BASE - IO_CPU_PHYS + IO_CPU_VIRT) #endif -#define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS + IO_PPSB_VIRT) +#ifdef CONFIG_HAVE_ARM_SCU #define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS + IO_CPU_VIRT) +#endif +#define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS + IO_PPSB_VIRT) #ifdef __ASSEMBLY__ @@ -96,6 +98,7 @@ bic \tmp1, \tmp1, #(1<<6) | (1<<0) @ clear ACTLR.SMP | ACTLR.FW mcr p15, 0, \tmp1, c1, c0, 1 @ ACTLR isb +#ifdef CONFIG_HAVE_ARM_SCU cpu_id \tmp1 mov \tmp1, \tmp1, lsl #2 mov \tmp2, #0xf @@ -103,6 +106,7 @@ mov32 \tmp1, TEGRA_ARM_PERIF_VIRT + 0xC str \tmp2, [\tmp1] @ invalidate SCU tags for CPU dsb +#endif .endm #define DEBUG_CONTEXT_STACK 0 |