ARM: tegra2: power: Fix reset race condition between the CPUs

During LP2 for CPU idle on Tegra2, there could be a race condition
between the CPUs. CPU1 cannot autonomously shut itself down (put
itself into reset). CPU1 must be reset by CPU0 but only when it
has no outstanding memory or I/O transactions going on (i.e., it
is in the WFI state). CPU1 indicates its readiness to be reset
by setting status in a PMC scratch register. If CPU1 wakes up
and CPU0 sees CPU1's ready to be reset status before CPU1 can
clear it CPU1 could be reset at inappropriate times resulting
in loss of cache coherency and ultimately a kernel panic.

Eliminate the race condition by ensuring that:

- CPU1's reset ready status is cleared as early as possible
  before CPU1 rejoins the coherent world.
- Use writel when updating the IRAM LP2 status flags to ensure
  the IRAM and coherent memory views of the flags are consistent.
- If there is not enough time remaining for CPU1 to be in LP2 for
  the minimum residency time, clear CPU1's reset status flag
  before entering WFI so that CPU0 will not wait for CPU1 to be
  ready to reset (since it won't be if there is insufficient time).

Change-Id: I20dc5c6406b1521f20852294d48ce6d67f0926b9
Signed-off-by: Scott Williams <scwilliams@nvidia.com>

Rebase-Id: Rd485f696126d7ca019d15651b839d4f2fc595848

1 files changed, 1 insertions, 0 deletions

diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index fcc6503d7e64..8f9926fe7172 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -206,6 +206,7 @@ extern void tegra2_iram_end;
 int  tegra2_cpu_is_resettable_soon(void);
 void tegra2_cpu_reset(int cpu);
 void tegra2_cpu_set_resettable_soon(void);
+void tegra2_cpu_clear_resettable(void);
 void tegra2_sleep_core(unsigned long v2p);
 void tegra2_hotplug_shutdown(void);
 void tegra2_sleep_wfi(unsigned long v2p);