diff options
| author | Alex Frid <afrid@nvidia.com> | 2013-07-24 13:51:38 -0700 |
|---|---|---|
| committer | Riham Haidar <rhaidar@nvidia.com> | 2013-07-26 15:25:13 -0700 |
| commit | b0600e1d87f2eb30acd0ebf58baef42288a7222f (patch) | |
| tree | 727a7b69568d6d8cc2db4e49cc942d7af82d739c /arch/arm/mach-tegra/tegra11_edp.c | |
| parent | b89c138498dfa8db157c9b23172f9da98ea9e583 (diff) | |
ARM: tegra11: power: Add AP40X core EDP tables
Bug 1326355
Change-Id: Ic6932da6da1aa83ce8582d68167ff50f8ea4663a
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/253186
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Andy Carman <acarman@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Rick Song <ricks@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/tegra11_edp.c')
| -rw-r--r-- | arch/arm/mach-tegra/tegra11_edp.c | 119 |
1 files changed, 118 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/tegra11_edp.c b/arch/arm/mach-tegra/tegra11_edp.c index f6c0a7e9c0fa..5b005e0e8315 100644 --- a/arch/arm/mach-tegra/tegra11_edp.c +++ b/arch/arm/mach-tegra/tegra11_edp.c @@ -640,6 +640,123 @@ static struct core_edp_entry core_edp_table[] = { }, }, }, + /* SKU 8 */ + { + .sku = 0x8, /* SKU = 8 */ + .process_id = -1, /* any process id */ + .cap_mA = 6000, /* 6A cap */ + .mult = 1000000, /* MHZ */ + .cap_scpu_on = { + /* favor emc */ + { /* core modules power state 0 (all ON) */ + {{ 744, 672 }, + { 744, 636 }, + { 744, 636 }, + { 744, 576 }, + }, + }, + /* balanced profile */ + { /* core modules power state 0 (all ON) */ + {{ 744, 672 }, + { 744, 636 }, + { 744, 636 }, + { 744, 576 }, + }, + }, + /* favor gpu */ + { /* core modules power state 0 (all ON) */ + {{ 744, 672 }, + { 624, 672 }, + { 624, 672 }, + { 624, 636 }, + } + }, + }, + .cap_scpu_off = { + /* favor emc */ + { /* core modules power state 0 (all ON) */ + {{ 744, 672 }, + { 744, 672 }, + { 744, 672 }, + { 744, 648 }, + }, + }, + /* balanced profile */ + { /* core modules power state 0 (all ON) */ + {{ 744, 672 }, + { 744, 672 }, + { 744, 672 }, + { 744, 648 }, + }, + }, + /* favor gpu */ + { /* core modules power state 0 (all ON) */ + {{ 744, 672 }, + { 744, 672 }, + { 744, 672 }, + { 744, 648 }, + } + }, + }, + }, + { + .sku = 0x8, /* SKU = 8 */ + .process_id = -1, /* any process id */ + .cap_mA = 8000, /* 8A cap */ + .mult = 1000000, /* MHZ */ + .cap_scpu_on = { + /* favor emc */ + { /* core modules power state 0 (all ON) */ + {{ 744, 672 }, + { 744, 672 }, + { 744, 672 }, + { 744, 648 }, + }, + }, + /* balanced profile */ + { /* core modules power state 0 (all ON) */ + {{ 744, 672 }, + { 744, 672 }, + { 744, 672 }, + { 744, 648 }, + }, + }, + /* favor gpu */ + { /* core modules power state 0 (all ON) */ + {{ 744, 672 }, + { 744, 672 }, + { 744, 672 }, + { 744, 648 }, + } + }, + }, + .cap_scpu_off = { + /* favor emc */ + { /* core modules power state 0 (all ON) */ + {{ 744, 672 }, + { 744, 672 }, + { 744, 672 }, + { 744, 648 }, + }, + }, + /* balanced profile */ + { /* core modules power state 0 (all ON) */ + {{ 744, 672 }, + { 744, 672 }, + { 744, 672 }, + { 744, 648 }, + }, + }, + /* favor gpu */ + { /* core modules power state 0 (all ON) */ + {{ 792, 828 }, + { 792, 816 }, + { 792, 804 }, + { 792, 648 }, + } + }, + }, + }, }; #ifdef CONFIG_TEGRA_EDP_LIMITS @@ -777,7 +894,7 @@ static struct core_edp_entry *find_edp_entry(int sku, unsigned int regulator_mA) if ((sku == 0x5) || (sku == 0x6)) { if (regulator_mA >= 8000) return NULL; /* no edp limits above 8A */ - } else if ((sku == 0x3) || (sku == 0x4)) { + } else if ((sku == 0x3) || (sku == 0x4) || (sku == 0x8)) { if (regulator_mA >= 8000) regulator_mA = 8000; /* apply 8A table above 8A */ } else { |