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authorAlex Frid <afrid@nvidia.com>2012-12-10 17:13:35 -0800
committerRohan Somvanshi <rsomvanshi@nvidia.com>2012-12-18 05:32:44 -0800
commit6befd012cb0e3fdb42e9a89b0bdfcc415dc594ba (patch)
tree34e9e73506687cb987492057acd1965f70b061cd /arch/arm/mach-tegra/tegra11_emc.c
parente0af21c3af29909b507059840983071b3ca24dc5 (diff)
ARM: tegra11: clock: Don't preset EMC VREF bits
Don't preset VREF bits in XM2DQSPADCTRL3 registers during EMC clock change procedure. Change-Id: I3abb6d07d93632b61363e2b0f7de37e1d7312af0 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/169874 (cherry picked from commit f44c79f042d50faca3da3e00add786ee29119624) Reviewed-on: http://git-master/r/171625 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/tegra11_emc.c')
-rw-r--r--arch/arm/mach-tegra/tegra11_emc.c2
1 files changed, 0 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/tegra11_emc.c b/arch/arm/mach-tegra/tegra11_emc.c
index 9050ee02edb5..9d095bdca982 100644
--- a/arch/arm/mach-tegra/tegra11_emc.c
+++ b/arch/arm/mach-tegra/tegra11_emc.c
@@ -404,8 +404,6 @@ static inline bool dqs_preset(const struct tegra11_emc_table *next_timing,
} while (0)
DQS_SET(XM2DQSPADCTRL2, VREF);
- DQS_SET_TRIM(XM2DQSPADCTRL3, VREF, 0);
- DQS_SET_TRIM(XM2DQSPADCTRL3, VREF, 1);
return ret;
}