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author | Alex Frid <afrid@nvidia.com> | 2013-11-04 23:00:55 -0800 |
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committer | Yu-Huan Hsu <yhsu@nvidia.com> | 2013-11-18 12:54:14 -0800 |
commit | 7c29d79886127f798a871dd4ce30246796a47c7c (patch) | |
tree | 56e4e7d251488351197943957a042a0601c7a894 /arch/arm/mach-tegra/tegra12_clocks.c | |
parent | 5203204d2d22e537da7d10ff035dec50342cee6d (diff) |
ARM: tegra12: dvfs: Update GPU DVFS table
Added GPU speedo id 0x2 (frequency limit 1.032GHz) and the resepctive
CVB entries for high GPU frequencies.
Bug 1342499
Change-Id: Ia2c009b925ca7215d9e97f925c8dbcf7f37a9bb4
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/327008
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/tegra12_clocks.c')
0 files changed, 0 insertions, 0 deletions