diff options
| author | Krishna Sitaraman <ksitaraman@nvidia.com> | 2014-01-14 11:05:17 -0800 |
|---|---|---|
| committer | Thomas Cherry <tcherry@nvidia.com> | 2014-02-04 14:53:39 -0800 |
| commit | b2c5073a4b5618a7fb5955d2a0ea415a7a40fdbc (patch) | |
| tree | 646d3b7bccd5223f7ec1d464807adda1446a3f2b /arch/arm/mach-tegra/tegra12_clocks.c | |
| parent | 6accf4cbf8ff9e86354919da4dde7e9c3e9efe2c (diff) | |
ARM: T132: Clocks: Update PLLDP initialization routine
If BootLoader initialized PLLDP skip re-initilization.
Bug 1439061
Change-Id: I0e188b20febf4e81f9442c60a3c304d5c13cf466
Reviewed-on: http://git-master/r/355589
Signed-off-by: Krishna Sitaraman <ksitaraman@nvidia.com>
Reviewed-on: http://git-master/r/361694
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
Tested-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/tegra12_clocks.c')
| -rw-r--r-- | arch/arm/mach-tegra/tegra12_clocks.c | 36 |
1 files changed, 18 insertions, 18 deletions
diff --git a/arch/arm/mach-tegra/tegra12_clocks.c b/arch/arm/mach-tegra/tegra12_clocks.c index c82751019e4e..7b37961db6dc 100644 --- a/arch/arm/mach-tegra/tegra12_clocks.c +++ b/arch/arm/mach-tegra/tegra12_clocks.c @@ -3704,25 +3704,26 @@ static void tegra12_pllss_clk_init(struct clk *c) c->min_rate = DIV_ROUND_UP(c->u.pll.vco_min, pllss_p[PLLSS_SW_PDIV_MAX]); - /* Assuming bootloader does not initialize these PLLs */ - n = (val & PLLSS_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT; - BUG_ON(n > 1); + c->state = (val & PLL_BASE_ENABLE) ? ON : OFF; - /* Reset default value of those PLLs are not safe. - For example, they cause problem in LP0 resume. - Replace them here with the safe value. */ - m = PLL_FIXED_MDIV(c, input_rate); - n = c->u.pll.vco_min / input_rate * m; - p_div = PLLSS_SW_PDIV_MAX; - val &= ~PLLSS_BASE_DIVM_MASK; - val &= ~PLLSS_BASE_DIVN_MASK; - val &= ~PLLSS_BASE_DIVP_MASK; - val |= m << PLL_BASE_DIVM_SHIFT; - val |= n << PLL_BASE_DIVN_SHIFT; - val |= p_div << PLL_BASE_DIVP_SHIFT; - clk_writel(val, c->reg + PLL_BASE); + if (c->state == OFF){ + /* Reset default value of those PLLs are not safe. + For example, they cause problem in LP0 resume. + Replace them here with the safe value. */ + m = PLL_FIXED_MDIV(c, input_rate); + n = c->u.pll.vco_min / input_rate * m; + p_div = PLLSS_SW_PDIV_MAX; + val &= ~PLLSS_BASE_DIVM_MASK; + val &= ~PLLSS_BASE_DIVN_MASK; + val &= ~PLLSS_BASE_DIVP_MASK; + val |= m << PLL_BASE_DIVM_SHIFT; + val |= n << PLL_BASE_DIVN_SHIFT; + val |= p_div << PLL_BASE_DIVP_SHIFT; + clk_writel(val, c->reg + PLL_BASE); - c->state = (val & PLL_BASE_ENABLE) ? ON : OFF; + pllss_set_defaults(c, input_rate); + } else + pr_info("%s was initialized by BootLoader\n", c->name); m = (val & PLLSS_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT; n = (val & PLLSS_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT; @@ -3735,7 +3736,6 @@ static void tegra12_pllss_clk_init(struct clk *c) pr_info("%s: val=%08x m=%d n=%d p_div=%d input_rate=%lu\n", c->name, val, m, n, p_div, input_rate); - pllss_set_defaults(c, input_rate); } static int tegra12_pllss_clk_enable(struct clk *c) |