diff options
| author | Alex Frid <afrid@nvidia.com> | 2014-01-16 22:07:21 -0800 |
|---|---|---|
| committer | Yu-Huan Hsu <yhsu@nvidia.com> | 2014-01-17 14:46:59 -0800 |
| commit | b9a322c2ca320c4a30a7991226a1646fc340e485 (patch) | |
| tree | caf0d48068734d88e6dfd407ccf6211246ad03d4 /arch/arm/mach-tegra/tegra12_clocks.c | |
| parent | 5bf5a77113c0451e1cc3036945babe0c00e4b3ad (diff) | |
ARM: tegra: dvfs: Set DFLL clock data in common code
Set CL-DVFS data for DFLL target clock by CL-DVFS driver probe code
(instead of per-chip DFLL clock initialization).
Change-Id: I742093570245f6ef97dfdc908c538de6ff4c338e
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/356964
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/tegra12_clocks.c')
| -rw-r--r-- | arch/arm/mach-tegra/tegra12_clocks.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/tegra12_clocks.c b/arch/arm/mach-tegra/tegra12_clocks.c index c686b43d5bc5..57233b1e76eb 100644 --- a/arch/arm/mach-tegra/tegra12_clocks.c +++ b/arch/arm/mach-tegra/tegra12_clocks.c @@ -4030,7 +4030,6 @@ static void __init tegra12_dfll_cpu_late_init(struct clk *c) ret = tegra_init_cl_dvfs(); if (!ret) { c->state = OFF; - c->u.dfll.cl_dvfs = platform_get_drvdata(&tegra_cl_dvfs_device); if (tegra_platform_is_silicon()) use_dfll = CONFIG_TEGRA_USE_DFLL_RANGE; tegra_dvfs_set_dfll_range(cpu->dvfs, use_dfll); |