diff options
| author | Bibek Basu <bbasu@nvidia.com> | 2014-11-06 16:34:09 +0530 |
|---|---|---|
| committer | Winnie Hsu <whsu@nvidia.com> | 2014-11-21 13:46:32 -0800 |
| commit | e9b32d4342a9ee9308729ae0c725d421869a0538 (patch) | |
| tree | b75923e1184e8620e4a7e8650b306fb96d606d9c /arch/arm/mach-tegra/tegra12_dvfs.c | |
| parent | 2c1ad0be0a4ef9a83f8fbdbb19dbc72cb83f7420 (diff) | |
arm: tegra12: add support for CD575M 24x7 Chip
Added DVFS support for CD575M Always on behaviour.
With this personality configuration for the chip,the
lifetime of the chip increases to 5 Yrs
Operating Temp : -25 to 105 degC
CPU DVFS: Max Freq 1938Mhz. Max Voltage 1.12V
SOC DVFS: Max Voltage0 1.01V EMC dvfs max freq 792Mhz
GPU DVFS: Max Freq 804Mhz and Ma Voltage 1.09V
Bug 1563635
Change-Id: If7fec38b83ae4de8c5435006207fa3cf717384c0
Signed-off-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-on: http://git-master/r/594855
GVS: Gerrit_Virtual_Submit
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/tegra12_dvfs.c')
| -rw-r--r-- | arch/arm/mach-tegra/tegra12_dvfs.c | 36 |
1 files changed, 18 insertions, 18 deletions
diff --git a/arch/arm/mach-tegra/tegra12_dvfs.c b/arch/arm/mach-tegra/tegra12_dvfs.c index a5d37ddb73d9..ac59d2c0a4a2 100644 --- a/arch/arm/mach-tegra/tegra12_dvfs.c +++ b/arch/arm/mach-tegra/tegra12_dvfs.c @@ -152,8 +152,8 @@ void __init tegra12x_vdd_cpu_align(int step_uv, int offset_uv) /* CPU DVFS tables */ static unsigned long cpu_max_freq[] = { -/* speedo_id 0 1 2 3 4 5 */ - 2014500, 2320500, 2116500, 2524500, 1811000, 2218500, +/* speedo_id 0 1 2 3 4 5 6 */ + 2014500, 2320500, 2116500, 2524500, 1811000, 2218500, 1938000, }; static struct cpu_cvb_dvfs cpu_cvb_dvfs_table[] = { @@ -277,11 +277,24 @@ static const int core_millivolts[MAX_DVFS_FREQS] = { .dvfs_rail = &tegra12_dvfs_rail_vdd_core, \ } +#define DEFER_DVFS(_clk_name, _speedo_id, _process_id, _auto, _mult, _freqs...) \ + { \ + .clk_name = _clk_name, \ + .speedo_id = _speedo_id, \ + .process_id = _process_id, \ + .freqs = {_freqs}, \ + .freqs_mult = _mult, \ + .millivolts = core_millivolts, \ + .auto_dvfs = _auto, \ + .defer_override = true, \ + .dvfs_rail = &tegra12_dvfs_rail_vdd_core, \ + } + static struct dvfs core_dvfs_table[] = { /* Core voltages (mV): 800, 850, 900, 950, 1000, 1050, 1100, 1110, 1150 */ /* Clock limits for internal blocks, PLLs */ - CORE_DVFS("emc", -1, -1, 1, KHZ, 264000, 348000, 384000, 384000, 528000, 528000, 1200000, 1200000, 1200000), + CORE_DVFS("emc", -1, -1, 1, KHZ, 264000, 348000, 384000, 384000, 792000, 792000, 1200000, 1200000, 1200000), CORE_DVFS("cpu_lp", 0, 0, 1, KHZ, 312000, 528000, 660000, 804000, 912000, 1044000, 1044000, 1044000, 1044000), CORE_DVFS("cpu_lp", 0, 1, 1, KHZ, 312000, 564000, 696000, 828000, 960000, 1044000, 1044000, 1044000, 1044000), @@ -440,19 +453,6 @@ static struct dvfs core_dvfs_table_automotive[] = { * clock capabilities specified in DVFS table. * */ -#define DEFER_DVFS(_clk_name, _speedo_id, _process_id, _auto, _mult, _freqs...) \ - { \ - .clk_name = _clk_name, \ - .speedo_id = _speedo_id, \ - .process_id = _process_id, \ - .freqs = {_freqs}, \ - .freqs_mult = _mult, \ - .millivolts = core_millivolts, \ - .auto_dvfs = _auto, \ - .defer_override = true, \ - .dvfs_rail = &tegra12_dvfs_rail_vdd_core, \ - } - static struct dvfs disp_dvfs_table[] = { /* * The clock rate for the display controllers that determines the @@ -478,8 +478,8 @@ static int resolve_core_override(int min_override_mv) /* GPU DVFS tables */ static unsigned long gpu_max_freq[] = { -/* speedo_id 0 1 2 3 */ - 648000, 852000, 1008000, 600000 +/* speedo_id 0 1 2 3 4 */ + 648000, 852000, 1008000, 600000, 804000 }; static struct gpu_cvb_dvfs gpu_cvb_dvfs_table[] = { { |