diff options
| author | Diwakar Tundlam <dtundlam@nvidia.com> | 2014-04-08 12:31:33 -0700 |
|---|---|---|
| committer | Diwakar Tundlam <dtundlam@nvidia.com> | 2014-04-09 16:49:58 -0700 |
| commit | 5f5aa920ea6594462fce367e1e838f74f6a93565 (patch) | |
| tree | 4109cf6c9254f142a2239b7a2fdd0d9fe7314c77 /arch/arm/mach-tegra/tegra12_edp.c | |
| parent | e049b135330e097093a7f30023e90b8fb3ac2379 (diff) | |
arm: tegra13: prepare to add EDP support
Refactor EDP code in preparation for adding T13x EDP support
(VDD_CPU and VDD_GPU) in order to reuse code that is common
between T12x and T13x.
Bug 1434482
Change-Id: I0a4fd70f9ae8fc4516d10250ed60cbbd502ce0f2
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/393656
GVS: Gerrit_Virtual_Submit
Reviewed-by: Timo Alho <talho@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/tegra12_edp.c')
| -rw-r--r-- | arch/arm/mach-tegra/tegra12_edp.c | 88 |
1 files changed, 44 insertions, 44 deletions
diff --git a/arch/arm/mach-tegra/tegra12_edp.c b/arch/arm/mach-tegra/tegra12_edp.c index 84f026618ce1..dadd16585a6c 100644 --- a/arch/arm/mach-tegra/tegra12_edp.c +++ b/arch/arm/mach-tegra/tegra12_edp.c @@ -262,37 +262,37 @@ static struct core_edp_entry core_edp_table[] = { #ifdef CONFIG_TEGRA_EDP_LIMITS #define LEAKAGE_CONSTS_IJK_COMMON \ -{ \ - /* i = 0 */ \ +{ \ + /* i = 0 */ \ { { -309609464, 197786326, -40763150, 1613941, }, \ { 964716269, -569081375, 115781607, -4206296, }, \ { -994324790, 529664031, -106360108, 3454033, }, \ { 343209442, -160577505, 31928605, -895157, }, \ - }, \ - /* i = 1 */ \ + }, \ + /* i = 1 */ \ { { 616319664, -637007187, 137759592, -7194133, }, \ { -1853817283, 1896032851, -407407611, 20868220, }, \ { 1824097131, -1831611624, 390753403, -19530122, }, \ { -589155245, 578838526, -122655676, 5985577, }, \ - }, \ - /* i = 2 */ \ + }, \ + /* i = 2 */ \ { { -439994037, 455845250, -104097013, 6191899, }, \ { 1354650774, -1395561938, 318665647, -18886906, }, \ { -1361677255, 1390149678, -317474532, 18728266, }, \ { 447877887, -451382027, 103201434, -6046692, }, \ - }, \ - /* i = 3 */ \ + }, \ + /* i = 3 */ \ { { 56797556, -59779544, 13810295, -848290, }, \ { -175867301, 184753957, -42708242, 2621537, }, \ { 177626357, -185996541, 43029384, -2638283, }, \ { -58587547, 61075322, -14145853, 865351, }, \ - }, \ + }, \ } #define EDP_PARAMS_COMMON_PART \ .temp_scaled = 10, \ .dyn_scaled = 1000, \ - .dyn_consts_n = { 950, 1399, 2166, 3041 }, \ + .dyn_consts_n = { 950, 1399, 2166, 3041 }, \ .consts_scaled = 100, \ .leakage_consts_n = { 45, 67, 87, 100 }, \ .ijk_scaled = 100000, \ @@ -325,42 +325,42 @@ static struct tegra_edp_cpu_leakage_params t12x_leakage_params[] = { #ifdef CONFIG_TEGRA_GPU_EDP static struct tegra_edp_gpu_leakage_params t12x_gpu_leakage_params = { - .temp_scaled = 10, - .dyn_scaled = 1000, - .dyn_consts_n = 10646, - .consts_scaled = 1, - .leakage_consts_n = 1, - .ijk_scaled = 100000, - .leakage_consts_ijk = { - /* i = 0 */ - { { -208796792, 37746202, -9648869, 725660, }, - { 704446675, -133808535, 34470023, -2464142, }, - { -783701649, 146557393, -38623024, 2654269, }, - { 292709580, -51246839, 13984499, -934964, }, - }, - /* i = 1 */ - { { 115095343, -65602614, 11251896, -838394, }, - { -394753929, 263095142, -49006854, 3326269, }, - { 441644020, -313320338, 61612126, -3916786, }, - { -164021554, 118634317, -24406245, 1517573, }, - }, - /* i = 2 */ - { { -38857760, 12243796, -1964159, 181232, }, - { 143265078, -71110695, 13985680, -917947, }, - { -171456530, 98906114, -21261015, 1216159, }, - { 67437536, -40520060, 9265259, -484818, }, - }, - /* i = 3 */ - { { 1795940, -345535, 83004, -20007, }, - { -8549105, 6333235, -1479815, 115441, }, - { 12192546, -10880741, 2632212, -161404, }, - { -5328587, 4953756, -1215038, 64556, }, - }, - }, - .leakage_min = 30, + .temp_scaled = 10, + .dyn_scaled = 1000, + .dyn_consts_n = 10646, + .consts_scaled = 1, + .leakage_consts_n = 1, + .ijk_scaled = 100000, + .leakage_consts_ijk = { + /* i = 0 */ + { { -208796792, 37746202, -9648869, 725660, }, + { 704446675, -133808535, 34470023, -2464142, }, + { -783701649, 146557393, -38623024, 2654269, }, + { 292709580, -51246839, 13984499, -934964, }, + }, + /* i = 1 */ + { { 115095343, -65602614, 11251896, -838394, }, + { -394753929, 263095142, -49006854, 3326269, }, + { 441644020, -313320338, 61612126, -3916786, }, + { -164021554, 118634317, -24406245, 1517573, }, + }, + /* i = 2 */ + { { -38857760, 12243796, -1964159, 181232, }, + { 143265078, -71110695, 13985680, -917947, }, + { -171456530, 98906114, -21261015, 1216159, }, + { 67437536, -40520060, 9265259, -484818, }, + }, + /* i = 3 */ + { { 1795940, -345535, 83004, -20007, }, + { -8549105, 6333235, -1479815, 115441, }, + { 12192546, -10880741, 2632212, -161404, }, + { -5328587, 4953756, -1215038, 64556, }, + }, + }, + .leakage_min = 30, }; -struct tegra_edp_gpu_leakage_params *tegra12x_get_gpu_leakage_params() +struct tegra_edp_gpu_leakage_params *tegra12x_get_gpu_leakage_params(void) { return &t12x_gpu_leakage_params; } |