diff options
| author | Prashant Gaikwad <pgaikwad@nvidia.com> | 2011-05-25 10:00:33 +0530 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:42:42 -0800 |
| commit | 11f4e7f8ad92c56fd003b07a19dfc4bacbfc014e (patch) | |
| tree | 8aacc88cf6c55ebe997129665949424e8ab5b6e3 /arch/arm/mach-tegra/tegra2_clocks.c | |
| parent | 382e01066b38ef87f3bcd213455cae2cc3dfac93 (diff) | |
ARM: tegra: clocks: init shared clk after sku limit
shared clock rate is dependent on its parent max rate. Parent's max rate
get updated in sku limit init depending on the sku value. Hence initialize
shared clocks after sku limits are applied.
Bug 821534
Original-Change-Id: I505b03bc03702c198f07f36437b2e9f3fc8e50cb
Reviewed-on: http://git-master/r/29803
Tested-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Rebase-Id: Rd20682be06b2edec9acdfc8fd0b6f110dfc94166
Diffstat (limited to 'arch/arm/mach-tegra/tegra2_clocks.c')
| -rw-r--r-- | arch/arm/mach-tegra/tegra2_clocks.c | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c index 72610ef037d3..72b3ab578aa5 100644 --- a/arch/arm/mach-tegra/tegra2_clocks.c +++ b/arch/arm/mach-tegra/tegra2_clocks.c @@ -2262,7 +2262,7 @@ static struct clk tegra_clk_emc = { .parent = _parent, \ } -struct clk tegra_list_clks[] = { +struct clk tegra_list_periph_clks[] = { PERIPH_CLK("apbdma", "tegra-dma", NULL, 34, 0, 0x31E, 108000000, mux_pclk, 0), PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 0x31E, 32768, mux_clk_32k, PERIPH_NO_RESET), PERIPH_CLK("kbc", "tegra-kbc", NULL, 36, 0, 0x31E, 32768, mux_clk_32k, PERIPH_NO_RESET), @@ -2330,7 +2330,9 @@ struct clk tegra_list_clks[] = { PERIPH_CLK("afi", NULL, "afi", 72, 0, 0x31E, 26000000, mux_clk_m, PERIPH_MANUAL_RESET), PERIPH_CLK("pcie_xclk", NULL, "pcie_xclk", 74, 0, 0x31E, 26000000, mux_clk_m, PERIPH_MANUAL_RESET), PERIPH_CLK("stat_mon", "tegra-stat-mon", NULL, 37, 0, 0x31E, 26000000, mux_clk_m, 0), +}; +struct clk tegra_list_shared_clks[] = { SHARED_CLK("avp.sclk", "tegra-avp", "sclk", &tegra_clk_virtual_sclk), SHARED_CLK("bsea.sclk", "tegra-aes", "sclk", &tegra_clk_virtual_sclk), SHARED_CLK("usbd.sclk", "fsl-tegra-udc", "sclk", &tegra_clk_virtual_sclk), @@ -2725,8 +2727,8 @@ void __init tegra_soc_init_clocks(void) for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++) tegra2_init_one_clock(tegra_ptr_clks[i]); - for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++) - tegra2_init_one_clock(&tegra_list_clks[i]); + for (i = 0; i < ARRAY_SIZE(tegra_list_periph_clks); i++) + tegra2_init_one_clock(&tegra_list_periph_clks[i]); for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) { c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name); @@ -2743,5 +2745,8 @@ void __init tegra_soc_init_clocks(void) init_audio_sync_clock_mux(); tegra2_init_sku_limits(); + for (i = 0; i < ARRAY_SIZE(tegra_list_shared_clks); i++) + tegra2_init_one_clock(&tegra_list_shared_clks[i]); + register_syscore_ops(&tegra_clk_syscore_ops); } |