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authorColin Cross <ccross@android.com>2010-11-03 16:32:15 -0700
committerColin Cross <ccross@android.com>2010-11-03 17:55:55 -0700
commitc41283c28bf8296cfe27f843a7fa287b4d2ab9dd (patch)
tree1845975838b960ab9083c765482966bed04543d2 /arch/arm/mach-tegra/tegra2_clocks.c
parent34661b64da75b9990bcbee61203ea2fb76669625 (diff)
ARM: tegra: clock: Add a pass-through set_rate to super clocks
Change-Id: I55027c93415a59cbf701b1f30e436203316c0d61 Signed-off-by: Colin Cross <ccross@android.com>
Diffstat (limited to 'arch/arm/mach-tegra/tegra2_clocks.c')
-rw-r--r--arch/arm/mach-tegra/tegra2_clocks.c13
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index 8bc46e7e0988..2c667fab39ab 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -351,11 +351,24 @@ static int tegra2_super_clk_set_parent(struct clk *c, struct clk *p)
return -EINVAL;
}
+/*
+ * Super clocks have "clock skippers" instead of dividers. Dividing using
+ * a clock skipper does not allow the voltage to be scaled down, so instead
+ * adjust the rate of the parent clock. This requires that the parent of a
+ * super clock have no other children, otherwise the rate will change
+ * underneath the other children.
+ */
+static int tegra2_super_clk_set_rate(struct clk *c, unsigned long rate)
+{
+ return clk_set_rate(c->parent, rate);
+}
+
static struct clk_ops tegra_super_ops = {
.init = tegra2_super_clk_init,
.enable = tegra2_super_clk_enable,
.disable = tegra2_super_clk_disable,
.set_parent = tegra2_super_clk_set_parent,
+ .set_rate = tegra2_super_clk_set_rate,
};
/* virtual cpu clock functions */