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authorAlex Frid <afrid@nvidia.com>2011-01-22 23:16:44 -0800
committerDan Willemsen <dwillemsen@nvidia.com>2011-11-30 21:41:57 -0800
commitb85f76575eadcad4efb85400edbd583d6de5d8af (patch)
tree5e7ea4fcadbf23474caa056ac19d1cb50a834e0b /arch/arm/mach-tegra/tegra2_dvfs.c
parentf3162c3f241b9228a9f3d2757609b9859d47e694 (diff)
ARM: tegra: dvfs: Update MPE dvfs table
Updated MPE clock dvfs table with recent characterization data. As a result MPE clock limit is increased to 300MHz across all tegra 2 SKUs. Original-Change-Id: Ibe700770c7d109a397cb140b6f217a8d48509ff1 Reviewed-on: http://git-master/r/16662 Reviewed-by: Amit Kamath <akamath@nvidia.com> Tested-by: Amit Kamath <akamath@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Rebase-Id: R6e5c6cef46a05527a31d70ed87c6d3f58077c5e7
Diffstat (limited to 'arch/arm/mach-tegra/tegra2_dvfs.c')
-rw-r--r--arch/arm/mach-tegra/tegra2_dvfs.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/tegra2_dvfs.c b/arch/arm/mach-tegra/tegra2_dvfs.c
index fa45fa8ed039..34a62192346a 100644
--- a/arch/arm/mach-tegra/tegra2_dvfs.c
+++ b/arch/arm/mach-tegra/tegra2_dvfs.c
@@ -221,7 +221,11 @@ static struct dvfs dvfs_init[] = {
CORE_DVFS("3d", 2, 1, KHZ, 218500, 256500, 323000, 380000, 380000, 400000, 400000),
CORE_DVFS("3d", 3, 1, KHZ, 247000, 285000, 351500, 400000, 400000, 400000, 400000),
- CORE_DVFS("mpe", -1, 1, KHZ, 104500, 152000, 228000, 250000, 250000, 250000, 250000),
+ CORE_DVFS("mpe", 0, 1, KHZ, 104500, 152000, 228000, 300000, 300000, 300000, 300000),
+ CORE_DVFS("mpe", 1, 1, KHZ, 142500, 190000, 275500, 300000, 300000, 300000, 300000),
+ CORE_DVFS("mpe", 2, 1, KHZ, 190000, 237500, 300000, 300000, 300000, 300000, 300000),
+ CORE_DVFS("mpe", 3, 1, KHZ, 228000, 266000, 300000, 300000, 300000, 300000, 300000),
+
CORE_DVFS("vi", -1, 1, KHZ, 85000, 100000, 150000, 150000, 150000, 150000, 150000),
CORE_DVFS("sclk", 0, 1, KHZ, 95000, 133000, 190000, 222500, 240000, 247000, 262000),