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authorColin Cross <ccross@android.com>2010-10-26 20:33:24 -0700
committerColin Cross <ccross@android.com>2010-10-26 21:05:08 -0700
commit93198982100b0b04c84dad68bc13de2e807249c9 (patch)
tree86936c428207238343c0c4d282f47b38612b2f15 /arch/arm/mach-tegra/tegra2_dvfs.c
parent157e610c36957f0887ec0974e3ab2242e91894ee (diff)
ARM: tegra: dvfs: hdmi can not be an auto dvfs clock
The hdmi block contains a divider that is not visible to the clock subsystem, prevent auto dvfs on it so that clk_set_rate can set the input clock higher than 148.5 MHz. Change-Id: I7f09f4d099e2f24166a65b1b582fe16c1451deba Signed-off-by: Colin Cross <ccross@android.com>
Diffstat (limited to 'arch/arm/mach-tegra/tegra2_dvfs.c')
-rw-r--r--arch/arm/mach-tegra/tegra2_dvfs.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/tegra2_dvfs.c b/arch/arm/mach-tegra/tegra2_dvfs.c
index 854bb77107df..4f56fb88fc17 100644
--- a/arch/arm/mach-tegra/tegra2_dvfs.c
+++ b/arch/arm/mach-tegra/tegra2_dvfs.c
@@ -95,7 +95,6 @@ static struct dvfs dvfs_init[] = {
CORE_DVFS("pcie", 1, KHZ, 0, 0, 0, 250000, 250000),
CORE_DVFS("dsi", 1, KHZ, 100000, 100000, 100000, 500000, 500000),
CORE_DVFS("tvo", 1, KHZ, 0, 0, 0, 250000, 250000),
- CORE_DVFS("hdmi", 1, KHZ, 0, 0, 0, 148500, 148500),
/*
* The clock rate for the display controllers that determines the
@@ -105,6 +104,7 @@ static struct dvfs dvfs_init[] = {
*/
CORE_DVFS("disp1", 0, KHZ, 158000, 158000, 190000, 190000, 190000),
CORE_DVFS("disp2", 0, KHZ, 158000, 158000, 190000, 190000, 190000),
+ CORE_DVFS("hdmi", 0, KHZ, 0, 0, 0, 148500, 148500),
/*
* These clocks technically depend on the core process id,