diff options
| author | tkasivajhula <tkasivajhula@nvidia.com> | 2010-06-22 17:04:22 -0700 |
|---|---|---|
| committer | Yu-Huan Hsu <yhsu@nvidia.com> | 2010-06-30 20:22:13 -0700 |
| commit | 627fa473f742cf141a70298a9c366df07935fa2d (patch) | |
| tree | 2796277da9bc6ea00fe00858878707874b736722 /arch/arm/mach-tegra/tegra2_save.S | |
| parent | fdd7790b41ea281e50db197ff94f45ce342171b7 (diff) | |
[ARM/tegra] Various Fixes for the LP0 power state.tegra-9.12.15
- Fix the AVP suspend/restore path.
- KBC is currently broken as a wake up source, so disable that and enable rtc
- Fix warmboot sequence.
- Various other PMC issues
Change-Id: Ifa70b66253f3a30f85822ef6c0eecac29b1fc8d1
Reviewed-on: http://git-master/r/3019
Reviewed-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com>
Tested-by: Trivikram Kasivajhula <tkasivajhula@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/tegra2_save.S')
| -rw-r--r-- | arch/arm/mach-tegra/tegra2_save.S | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/tegra2_save.S b/arch/arm/mach-tegra/tegra2_save.S index 6f7fd086a366..b5353803e0b5 100644 --- a/arch/arm/mach-tegra/tegra2_save.S +++ b/arch/arm/mach-tegra/tegra2_save.S @@ -69,6 +69,9 @@ #define FLOW_CTRL_HALT_CPU_EVENTS 0x0 +#define DEBUG_FORCE_RTC_WAKEUP_SEC 0 +#define RTC_PA_BASE 0x7000e000 + #include "power-macros.S" .macro emc_device_mask, rd, base @@ -366,6 +369,33 @@ __tear_down_master_pll_cpu: bic r0, r0, #(1<<30) str r0, [r5, #CLK_RESET_PLLC_BASE] +#if DEBUG_FORCE_RTC_WAKEUP_SEC + //r0 = RTC_BASE + mov32 r0, RTC_PA_BASE + //setup rtc wake + ldr r2, [r0, #0x10] /* milli */ + ldr r2, [r0, #0x8] /* shadow */ + + add r2, r2, #DEBUG_FORCE_RTC_WAKEUP_SEC +rtc_idle1: + ldr r1, [r0, #0x4] + tst r1, #0x1 + bne rtc_idle1 + str r2, [r0, #0x14] +rtc_idle2: + ldr r1, [r0, #0x4] + tst r1, #0x1 + bne rtc_idle2 + /* intr mask alarm0 */ + mov r2, #1 + str r2, [r0, #0x28] + str r2, [r0, #0x2c] +rtc_idle3: + ldr r1, [r0, #0x4] + tst r1, #0x1 + bne rtc_idle3 +#endif + __cclk_burst_set: mov r0, #(4<<29) /* STOP_UNTIL_IRQ */ orr r0, r0, #(1<<10) | (1<<8) /* IRQ_0, FIQ_0 */ |