diff options
| author | Jihoon Bang <jbang@nvidia.com> | 2012-12-12 18:32:16 -0800 |
|---|---|---|
| committer | Rohan Somvanshi <rsomvanshi@nvidia.com> | 2012-12-20 05:57:26 -0800 |
| commit | e19fe03c9ed61149225622721ac25cb3a0e48e48 (patch) | |
| tree | e5842d7c77c7e67832bd1c45064c79e5273ff474 /arch/arm/mach-tegra/tegra30_clocks.c | |
| parent | e7db34e95ae88f41a137decd5dcb09b0bc91d1cf (diff) | |
ARM: tegra11: clock: change emc mode for mpe and msenc
Change msenc.emc and mpe.emc to have SHARED_BW
for mode. msenc or mpe client in user space will set
required memory bandwidth for module instead of emc clock
frequency because emc clock frequency can be affected
by many other clients and therefore it's impossible
for mpe or msenc to predict emc clock frequency as
SHARED_FLOOR.
Bug 1197543
Change-Id: I68237d0af75c13008cdc44fb55bc516980ebeaae
Signed-off-by: Jihoon Bang <jbang@nvidia.com>
Reviewed-on: http://git-master/r/170837
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/tegra30_clocks.c')
| -rw-r--r-- | arch/arm/mach-tegra/tegra30_clocks.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c index e6383eae6667..c2eca9fa0d62 100644 --- a/arch/arm/mach-tegra/tegra30_clocks.c +++ b/arch/arm/mach-tegra/tegra30_clocks.c @@ -4435,7 +4435,7 @@ struct clk tegra_list_clks[] = { SHARED_CLK("cap.emc", "cap.emc", NULL, &tegra_clk_emc, NULL, 0, SHARED_CEILING), SHARED_CLK("3d.emc", "tegra_gr3d", "emc", &tegra_clk_emc, NULL, 0, 0), SHARED_CLK("2d.emc", "tegra_gr2d", "emc", &tegra_clk_emc, NULL, 0, 0), - SHARED_CLK("mpe.emc", "tegra_mpe", "emc", &tegra_clk_emc, NULL, 0, 0), + SHARED_CLK("mpe.emc", "tegra_mpe", "emc", &tegra_clk_emc, NULL, 0, SHARED_BW), SHARED_CLK("camera.emc", "tegra_camera", "emc", &tegra_clk_emc, NULL, 0, SHARED_BW), SHARED_CLK("sdmmc4.emc", "sdhci-tegra.3", "emc", &tegra_clk_emc, NULL, 0, 0), SHARED_CLK("floor.emc", "floor.emc", NULL, &tegra_clk_emc, NULL, 0, 0), |