diff options
author | Kevin Huang <kevinh@nvidia.com> | 2011-07-26 17:49:43 -0700 |
---|---|---|
committer | Ryan Wong <ryanw@nvidia.com> | 2011-07-28 17:44:23 -0700 |
commit | 617434cebb5f6b7b6b6b72dea3df22ae92a897eb (patch) | |
tree | 97cb2179ffbe8d7e696144ea28643bfdecc7e7a0 /arch/arm/mach-tegra/tegra3_clocks.c | |
parent | 0810893fefc4c80e721b88259b9c8db582aa0248 (diff) |
ARM: tegra: clock: Optimize power consumption of DSI module DO NOT MERGE
- Disable phy clock at early suspend.
- Set DSI to LP mode at early suspend
Bug 847254
Bug 848069
Change-Id: Ia3199b1848075e7adfc3b8c686d93d4d5655aca5
Reviewed-on: http://git-master/r/43800
Reviewed-by: Chih-Lung Huang <lhuang@nvidia.com>
Tested-by: Chih-Lung Huang <lhuang@nvidia.com>
Reviewed-by: Ryan Wong <ryanw@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/tegra3_clocks.c')
-rw-r--r-- | arch/arm/mach-tegra/tegra3_clocks.c | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/arch/arm/mach-tegra/tegra3_clocks.c b/arch/arm/mach-tegra/tegra3_clocks.c index 00469a555fb9..05cbaa4148de 100644 --- a/arch/arm/mach-tegra/tegra3_clocks.c +++ b/arch/arm/mach-tegra/tegra3_clocks.c @@ -1348,12 +1348,6 @@ static int tegra3_pll_clk_enable(struct clk *c) val |= PLL_BASE_ENABLE; clk_writel(val, c->reg + PLL_BASE); - if (c->flags & PLLD) { - val = clk_readl(c->reg + PLL_MISC(c) + PLL_BASE); - val |= PLLD_MISC_CLKENABLE; - clk_writel(val, c->reg + PLL_MISC(c) + PLL_BASE); - } - if (c->flags & PLLM) { val = pmc_readl(PMC_PLLP_WB0_OVERRIDE_0); val |= PMC_PLLP_WB0_OVERRIDE_0_PLLM_ENABLE; @@ -1374,11 +1368,6 @@ static void tegra3_pll_clk_disable(struct clk *c) val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE); clk_writel(val, c->reg); - if (c->flags & PLLD) { - val = clk_readl(c->reg + PLL_MISC(c) + PLL_BASE); - val &= ~PLLD_MISC_CLKENABLE; - clk_writel(val, c->reg + PLL_MISC(c) + PLL_BASE); - } if (c->flags & PLLM) { val = pmc_readl(PMC_PLLP_WB0_OVERRIDE_0); val &= ~PMC_PLLP_WB0_OVERRIDE_0_PLLM_ENABLE; |