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authorAlex Frid <afrid@nvidia.com>2011-07-14 21:35:48 -0700
committerVarun Colbert <vcolbert@nvidia.com>2011-07-20 16:45:15 -0700
commit25be81288a8513e5af18fa50a21921034b30a70f (patch)
treec49b78c22f3cea9659931d075d58d436ae65e017 /arch/arm/mach-tegra/tegra3_clocks.c
parent30115e75f5398a755f0d2755a5a38e1d6894656d (diff)
ARM: tegra: clock: Set Tegra3 LPDDR2 minimum rate to 25MHz
Change-Id: I8cd5cfef8a040ffa5f0959b5a294b25a21fcfa8b Reviewed-on: http://git-master/r/41141 Reviewed-by: Varun Colbert <vcolbert@nvidia.com> Tested-by: Varun Colbert <vcolbert@nvidia.com>
Diffstat (limited to 'arch/arm/mach-tegra/tegra3_clocks.c')
-rw-r--r--arch/arm/mach-tegra/tegra3_clocks.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/tegra3_clocks.c b/arch/arm/mach-tegra/tegra3_clocks.c
index a238ef062743..c23a1211a2b8 100644
--- a/arch/arm/mach-tegra/tegra3_clocks.c
+++ b/arch/arm/mach-tegra/tegra3_clocks.c
@@ -3745,7 +3745,7 @@ static struct clk tegra_clk_emc = {
.ops = &tegra_emc_clk_ops,
.reg = 0x19c,
.max_rate = 800000000,
- .min_rate = 50000000,
+ .min_rate = 25000000,
.inputs = mux_pllm_pllc_pllp_clkm,
.flags = MUX | DIV_U71 | PERIPH_EMC_ENB,
.u.periph = {