diff options
| author | Alex Frid <afrid@nvidia.com> | 2012-01-09 19:46:25 -0800 |
|---|---|---|
| committer | Varun Colbert <vcolbert@nvidia.com> | 2012-01-20 13:56:42 -0800 |
| commit | 1faa1d5bd9db88b4e3656622ea81b48ca5b58367 (patch) | |
| tree | b76fa2fee4a7f777a84ea136018112443b51f09e /arch/arm/mach-tegra/tegra3_clocks.c | |
| parent | 937ed7672266b64988a86fdf30556f6fe75034da (diff) | |
ARM: tegra: clock: Add Tegra3 0.95V core voltage step
- Expanded Tegra3 DVFS tables with 0.95V core voltage step
- Updated cbus minimum rate calculation, since cbus can not
run at 0.95V
- Updated PLLM dvfs initialization, since PLLM can no longer
be voltage independent, even when its usage is restricted.
Bug 817679
Bug 841336
Change-Id: I4973dc19d351ce237f2b249ebf75a79abf3afef4
Reviewed-on: http://git-master/r/74141
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/76463
Reviewed-by: Automatic_Commit_Validation_User
Diffstat (limited to 'arch/arm/mach-tegra/tegra3_clocks.c')
| -rw-r--r-- | arch/arm/mach-tegra/tegra3_clocks.c | 19 |
1 files changed, 14 insertions, 5 deletions
diff --git a/arch/arm/mach-tegra/tegra3_clocks.c b/arch/arm/mach-tegra/tegra3_clocks.c index 3ed031fa5ac4..3fe531fe2e5b 100644 --- a/arch/arm/mach-tegra/tegra3_clocks.c +++ b/arch/arm/mach-tegra/tegra3_clocks.c @@ -2762,9 +2762,18 @@ static long tegra3_clk_cbus_round_rate(struct clk *c, unsigned long rate) if (!c->dvfs) return rate; - /* update min now, since no dvfs table was available during init */ - if (!c->min_rate) - c->min_rate = c->dvfs->freqs[0]; + /* update min now, since no dvfs table was available during init + (skip placeholder entries set to 1 kHz) */ + if (!c->min_rate) { + for (i = 0; i < (c->dvfs->num_freqs - 1); i++) { + if (c->dvfs->freqs[i] > 1 * c->dvfs->freqs_mult) { + c->min_rate = c->dvfs->freqs[i]; + break; + } + } + BUG_ON(!c->min_rate); + } + rate = max(rate, c->min_rate); for (i = 0; i < (c->dvfs->num_freqs - 1); i++) { unsigned long f = c->dvfs->freqs[i]; @@ -4168,9 +4177,9 @@ struct clk tegra_list_clks[] = { PERIPH_CLK("i2s2", "tegra30-i2s.2", "i2s", 18, 0x104, 26000000, mux_pllaout0_audio2_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), PERIPH_CLK("i2s3", "tegra30-i2s.3", "i2s", 101, 0x3bc, 26000000, mux_pllaout0_audio3_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), PERIPH_CLK("i2s4", "tegra30-i2s.4", "i2s", 102, 0x3c0, 26000000, mux_pllaout0_audio4_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("spdif_out", "tegra30-spdif", "spdif_out", 10, 0x108, 100000000, mux_pllaout0_audio_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), + PERIPH_CLK("spdif_out", "tegra30-spdif", "spdif_out", 10, 0x108, 26000000, mux_pllaout0_audio_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), PERIPH_CLK("spdif_in", "tegra30-spdif", "spdif_in", 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71 | PERIPH_ON_APB), - PERIPH_CLK("pwm", "pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_clk32_clkm, MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB), + PERIPH_CLK("pwm", "pwm", NULL, 17, 0x110, 408000000, mux_pllp_pllc_clk32_clkm, MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB), PERIPH_CLK("d_audio", "tegra30-ahub", "d_audio", 106, 0x3d0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71), PERIPH_CLK("dam0", "tegra30-dam.0", NULL, 108, 0x3d8, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71), PERIPH_CLK("dam1", "tegra30-dam.1", NULL, 109, 0x3dc, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71), |