diff options
| author | Alex Frid <afrid@nvidia.com> | 2011-04-05 16:45:05 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:42:30 -0800 |
| commit | 98c3a4ca47d49135f6b0d4c69598058e43643a74 (patch) | |
| tree | 79ef7d48878f711f49372683d37576e9991deb96 /arch/arm/mach-tegra/tegra3_emc.c | |
| parent | a23e89a919c2e95bb2e690312452e346de99b37e (diff) | |
ARM: tegra: clock: Modify EMC maximum rate settings
On A01 Tegra3 chip EMC rate may not reach full PLLM range - set
maximum EMC rate equal to boot rate. Use PLLM frequency as EMC
rate limit for A02+ chips.
Original-Change-Id: I0b901a29d628362b09f2a3d0ce908b4019804cfd
Reviewed-on: http://git-master/r/26786
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Original-Change-Id: I741fcfca646ba0a2a8732dbccaf7a2642d839809
Rebase-Id: R9b5913cccecc96221c1541887e6e3b03a8f1316a
Diffstat (limited to 'arch/arm/mach-tegra/tegra3_emc.c')
| -rw-r--r-- | arch/arm/mach-tegra/tegra3_emc.c | 20 |
1 files changed, 11 insertions, 9 deletions
diff --git a/arch/arm/mach-tegra/tegra3_emc.c b/arch/arm/mach-tegra/tegra3_emc.c index b4bf0755f197..2335d90504b8 100644 --- a/arch/arm/mach-tegra/tegra3_emc.c +++ b/arch/arm/mach-tegra/tegra3_emc.c @@ -695,10 +695,8 @@ static const struct clk_mux_sel *find_matching_input( /* Table entries specify rate in kHz */ inp_rate = clk_get_rate(sel->input) / 1000; - /* ddr duty cycle requires only 1:1 or 1:2k ratio */ - if ((inp_rate == table_rate) || - ((inp_rate >= 2*table_rate) && - (inp_rate % (2*table_rate) == 0))) { + if ((inp_rate >= table_rate) && + (inp_rate % table_rate == 0)) { *div_value = 2 * inp_rate / table_rate - 2; return sel; } @@ -710,8 +708,8 @@ void tegra_init_emc(const struct tegra_emc_table *table, int table_size) { int i; u32 reg, div_value; - bool pllm_entry = false; - unsigned long boot_rate; + bool max_entry = false; + unsigned long boot_rate, max_rate; const struct clk_mux_sel *sel; emc_stats.clkchange_count = 0; @@ -721,6 +719,7 @@ void tegra_init_emc(const struct tegra_emc_table *table, int table_size) emc = tegra_get_clock_by_name("emc"); BUG_ON(!emc); boot_rate = clk_get_rate(emc) / 1000; + max_rate = clk_get_max_rate(emc) / 1000; if (emc->parent != tegra_get_clock_by_name("pll_m")) { pr_warn("tegra: boot parent %s is not supported by EMC DFS\n", @@ -741,6 +740,9 @@ void tegra_init_emc(const struct tegra_emc_table *table, int table_size) if (table_rate == boot_rate) emc_last_sel = i; + if (table_rate == max_rate) + max_entry = true; + tegra_emc_clk_sel[i] = *sel; BUG_ON(div_value > (EMC_CLK_DIV_MASK >> EMC_CLK_DIV_SHIFT)); @@ -750,7 +752,6 @@ void tegra_init_emc(const struct tegra_emc_table *table, int table_size) if ((div_value == 0) && (tegra_emc_clk_sel[i].input == emc->parent)) { tegra_emc_clk_sel[i].value |= EMC_CLK_LOW_JITTER_ENABLE; - pllm_entry = true; } if (table[i].burst_regs[MC_EMEM_ARB_MISC0_INDEX] & @@ -771,8 +772,9 @@ void tegra_init_emc(const struct tegra_emc_table *table, int table_size) dram_dev_num = (mc_readl(MC_EMEM_ADR_CFG) & 0x1) + 1; /* 2 dev max */ - if (!pllm_entry) { - pr_err("tegra: invalid EMC DFS table: PLLM entry not found\n"); + if (!max_entry) { + pr_err("tegra: invalid EMC DFS table: entry for max rate" + " %lu kHz is not found\n", max_rate); return; } pr_info("tegra: validated EMC DFS table\n"); |