diff options
| author | Alex Frid <afrid@nvidia.com> | 2011-07-11 22:55:04 -0700 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:47:38 -0800 |
| commit | 3faad7cb45890ddeb6eeb3623fb289bfe583de42 (patch) | |
| tree | 1c622e036edb3dd71a5d058d4fd945441fd81eb4 /arch/arm/mach-tegra/tegra3_emc.c | |
| parent | 18163a0a7e1f99be1adaa97ff87b667c1247d397 (diff) | |
ARM: tegra: clock: Support Tegra3 EMC DFS table revision
Support Tegra3 EMC DFS table revision 3.1 that includes two additional
EMC shadow registers (reserved with previous table revision 3.0).
Bug 836260
Original-Change-Id: Ifea774ae862ea18aa6b81adda902714988a475fb
Reviewed-on: http://git-master/r/40749
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Tested-by: Raymond Poudrier <rapoudrier@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Rebase-Id: Rafa10bed9b6d6cef71986bbc97289dc02b18d478
Diffstat (limited to 'arch/arm/mach-tegra/tegra3_emc.c')
| -rw-r--r-- | arch/arm/mach-tegra/tegra3_emc.c | 24 |
1 files changed, 21 insertions, 3 deletions
diff --git a/arch/arm/mach-tegra/tegra3_emc.c b/arch/arm/mach-tegra/tegra3_emc.c index 1dc0a0f5d605..cbc0ad34784f 100644 --- a/arch/arm/mach-tegra/tegra3_emc.c +++ b/arch/arm/mach-tegra/tegra3_emc.c @@ -165,7 +165,10 @@ enum { DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_DA_TURNS) \ DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_DA_COVERS) \ DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_MISC0) \ - DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_RING1_THROTTLE) + DEFINE_REG(TEGRA_MC_BASE, MC_EMEM_ARB_RING1_THROTTLE) \ + \ + DEFINE_REG(TEGRA_EMC_BASE, EMC_FBIO_SPARE) \ + DEFINE_REG(TEGRA_EMC_BASE, EMC_CFG_RSV) #define DEFINE_REG(base, reg) ((base) ? ((u32)IO_ADDRESS((base)) + (reg)) : 0), static const u32 burst_reg_addr[TEGRA_EMC_NUM_REGS] = { @@ -179,6 +182,8 @@ enum { }; #undef DEFINE_REG +static int emc_num_burst_regs; + static struct clk_mux_sel tegra_emc_clk_sel[TEGRA_EMC_TABLE_MAX_SIZE]; static int emc_last_sel; static struct tegra_emc_table start_timing; @@ -475,7 +480,7 @@ static noinline void emc_set_clock(const struct tegra_emc_table *next_timing, auto_cal_disable(); /* 4. program burst shadow registers */ - for (i = 0; i < TEGRA_EMC_NUM_REGS; i++) { + for (i = 0; i < emc_num_burst_regs; i++) { if (!burst_reg_addr[i]) continue; __raw_writel(next_timing->burst_regs[i], burst_reg_addr[i]); @@ -577,7 +582,7 @@ static inline void emc_get_timing(struct tegra_emc_table *timing) { int i; - for (i = 0; i < TEGRA_EMC_NUM_REGS; i++) { + for (i = 0; i < emc_num_burst_regs; i++) { if (burst_reg_addr[i]) timing->burst_regs[i] = __raw_readl(burst_reg_addr[i]); else @@ -792,6 +797,19 @@ void tegra_init_emc(const struct tegra_emc_table *table, int table_size) } tegra_emc_table_size = min(table_size, TEGRA_EMC_TABLE_MAX_SIZE); + switch (table[0].rev) { + case 0x30: + emc_num_burst_regs = 105; + break; + case 0x31: + emc_num_burst_regs = 107; + break; + default: + pr_warn("tegra: invalid EMC DFS table: unknown rev 0x%x\n", + table[0].rev); + return; + } + for (i = 0; i < tegra_emc_table_size; i++) { unsigned long table_rate = table[i].rate; if (!table_rate) |