diff options
author | Diwakar Tundlam <dtundlam@nvidia.com> | 2011-06-22 21:17:19 -0700 |
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committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:48:10 -0800 |
commit | 4e8877b4267327db5a012e55a410ba69da550419 (patch) | |
tree | 3862c0f5eb102a155b67aee294558c60a1544fcb /arch/arm/mach-tegra/tegra3_speedo.c | |
parent | e7f18ba15667a2ee3cedbc39891095557f53c08d (diff) |
ARM: Tegra: dvfs: Added SKU definitions for AP33, T33, T33S
Original-Change-Id: Ib5432ef2ae023a370b751f8609d3dc7743f34bf1
Reviewed-on: http://git-master/r/46109
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
Rebase-Id: Rfde53d5c4d6819494d9c4484e76ab3febfc813a4
Diffstat (limited to 'arch/arm/mach-tegra/tegra3_speedo.c')
-rw-r--r-- | arch/arm/mach-tegra/tegra3_speedo.c | 43 |
1 files changed, 39 insertions, 4 deletions
diff --git a/arch/arm/mach-tegra/tegra3_speedo.c b/arch/arm/mach-tegra/tegra3_speedo.c index b91e96816b40..78dc0834a594 100644 --- a/arch/arm/mach-tegra/tegra3_speedo.c +++ b/arch/arm/mach-tegra/tegra3_speedo.c @@ -45,6 +45,11 @@ static const u32 core_process_speedos[][CORE_PROCESS_CORNERS_NUM] = { {170}, /* threshold_index 4: soc_speedo_id 1: AP30 char */ {190}, /* threshold_index 5: soc_speedo_id 2: T30 char */ {190}, /* threshold_index 6: soc_speedo_id 2: T30S char */ + +/* T33 family: Numbers cloned from T30 family; FIXME: adjust these later */ + {183}, /* threshold_index 7: soc_speedo_id = 1 - AP33 */ + {197}, /* threshold_index 8: soc_speedo_id = 2 - T33 */ + {197}, /* threshold_index 9: soc_speedo_id = 2 - T33S */ }; /* Maximum speedo levels for each CPU process corner */ @@ -61,6 +66,11 @@ static const u32 cpu_process_speedos[][CPU_PROCESS_CORNERS_NUM] = { {295, 326, 348, 364}, /* threshold_index 4: cpu_speedo_id 1: AP30char */ {326, 326, 348, 364}, /* threshold_index 5: cpu_speedo_id 2: T30char */ {326, 326, 348, 364}, /* threshold_index 6: cpu_speedo_id 3: T30Schar */ + +/* T33 family: Numbers cloned from T30 family; FIXME: adjust these later */ + {376, 376, 376, 376}, /* threshold_FIXME 7: cpu_speedo_id = 1 - AP33 */ + {376, 376, 376, 376}, /* threshold_index 8: cpu_speedo_id = 2 - T33 */ + {376, 376, 376, 376}, /* threshold_index 9: cpu_speedo_id = 3 - T33S */ }; /* @@ -114,6 +124,31 @@ static void rev_sku_to_speedo_ids(int rev, int sku) soc_speedo_id = 2; threshold_index = 2; break; + case 2: /* DSC => AP33 */ + cpu_speedo_id = 1; + soc_speedo_id = 1; + threshold_index = 7; + break; + default: + pr_err("Tegra3 Rev-A02: Reserved pkg: %d\n", + package_id); + BUG(); + break; + } + break; + + case 0x80: /* T33 or T33S */ + switch (package_id) { + case 1: /* MID => T33 */ + cpu_speedo_id = 2; + soc_speedo_id = 2; + threshold_index = 8; + break; + case 2: /* DSC => T33S */ + cpu_speedo_id = 3; + soc_speedo_id = 2; + threshold_index = 9; + break; default: pr_err("Tegra3 Rev-A02: Reserved pkg: %d\n", package_id); @@ -229,12 +264,12 @@ void tegra_init_speedo_data(void) core_process_id = iv -1; if (core_process_id == -1) { - pr_err("*****************************************************"); - pr_err("*****************************************************"); + pr_err("****************************************************"); + pr_err("****************************************************"); pr_err("* tegra3_speedo: CORE speedo value %3d out of range *", core_speedo_val); - pr_err("*****************************************************"); - pr_err("*****************************************************"); + pr_err("****************************************************"); + pr_err("****************************************************"); core_process_id = INVALID_PROCESS_ID; soc_speedo_id = 0; |