diff options
| author | Alex Frid <afrid@nvidia.com> | 2011-11-18 22:46:04 -0800 |
|---|---|---|
| committer | Dan Willemsen <dwillemsen@nvidia.com> | 2011-11-30 21:50:25 -0800 |
| commit | d2a1d360abc87215e6474334bdf395800b732020 (patch) | |
| tree | ef43b8c639d4ee91e1f7e1acec01578c7833d731 /arch/arm/mach-tegra/tegra3_speedo.c | |
| parent | 84a2d67dc80fe536d894854b7e29b6614accbfb5 (diff) | |
ARM: tegra: dvfs: Update Tegra3 xL speedo/nominal voltage
Updated Tegra3 xL core speedo and nominal voltage settings.
Re-factored nominal voltage selection, since new data introduced
dependency of core voltage on both CPU and core speedo id.
Bug 841336
Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 3330ce743434866502fd6b33d7d1718ec4ab4675)
(cherry picked from commit a9fb4cbc865e78706c72186ebac286506cd5b301)
Change-Id: I244df08153a6a275a2fe331c72e03d03f18a8ea1
Reviewed-on: http://git-master/r/67014
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Rebase-Id: Rd35cb9ac1fbcb424548e05d10d5622744394e796
Diffstat (limited to 'arch/arm/mach-tegra/tegra3_speedo.c')
| -rw-r--r-- | arch/arm/mach-tegra/tegra3_speedo.c | 39 |
1 files changed, 35 insertions, 4 deletions
diff --git a/arch/arm/mach-tegra/tegra3_speedo.c b/arch/arm/mach-tegra/tegra3_speedo.c index a0307ba33682..5c37fd3f3a84 100644 --- a/arch/arm/mach-tegra/tegra3_speedo.c +++ b/arch/arm/mach-tegra/tegra3_speedo.c @@ -52,8 +52,8 @@ static const u32 core_process_speedos[][CORE_PROCESS_CORNERS_NUM] = { {192}, /* [9]: soc_speedo_id = 2 - T33S */ /* T30 'L' family */ - {192}, /* [10]: soc_speedo_id 2: T30L */ - {192}, /* [11]: soc_speedo_id 2: T30SL */ + {192}, /* [10]: soc_speedo_id 1: T30L */ + {192}, /* [11]: soc_speedo_id 1: T30SL */ }; /* Maximum speedo levels for each CPU process corner */ @@ -170,7 +170,7 @@ static void rev_sku_to_speedo_ids(int rev, int sku) switch (package_id) { case 1: /* MID => T30L */ cpu_speedo_id = 7; - soc_speedo_id = 2; + soc_speedo_id = 1; threshold_index = 10; break; case 2: /* DSC => T30S */ @@ -188,7 +188,7 @@ static void rev_sku_to_speedo_ids(int rev, int sku) case 0x8F: /* T30SL */ cpu_speedo_id = 8; - soc_speedo_id = 2; + soc_speedo_id = 1; threshold_index = 11; break; @@ -340,3 +340,34 @@ int tegra_package_id(void) { return package_id; } + +/* + * CPU and core nominal voltage levels as determined by chip SKU and speedo + * (not final - can be lowered by dvfs tables and rail dependencies; the + * latter is resolved by the dvfs code) + */ +static const int cpu_speedo_nominal_millivolts[] = +/* speedo_id 0, 1, 2, 3, 4, 5, 6, 7, 8 */ + { 1125, 1150, 1150, 1150, 1237, 1237, 1237, 1150, 1150 }; + +int tegra_cpu_speedo_mv(void) +{ + BUG_ON(cpu_speedo_id >= ARRAY_SIZE(cpu_speedo_nominal_millivolts)); + return cpu_speedo_nominal_millivolts[cpu_speedo_id]; +} + +int tegra_core_speedo_mv(void) +{ + switch (soc_speedo_id) { + case 0: + return 1200; + case 1: + if ((cpu_speedo_id != 7) && (cpu_speedo_id != 8)) + return 1200; + /* fall thru for T30L or T30SL */ + case 2: + return 1300; + default: + BUG(); + } +} |